Wafer Level Chip Scale Package Encapsulant Rim
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Solution Overview
Problem
Wafer-level chip scale packaging (WLCSP) dies are brittle and prone to breakage during testing and board mounting due to the lack of an encapsulant, which compromises their robustness.
Innovation Solution
A method involving grinding the wafer backside to create a rim surrounding an inner portion, followed by applying an encapsulant over the inner portion, and optionally forming grooves or additional encapsulant on the active side to enhance singulation and thermal expansion matching with printed circuit boards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafer-level chip scale packaging is used to reduce package size, then package size is reduced to chip scale, but the die become brittle and prone to breakage due to lack of encapsulant
Solution Approach 1:
An encapsulant layer is applied over the backside of the die to provide mechanical protection and flexibility, preventing breakage during handling and mounting while maintaining the compact WLCSP form factor
Solution Approach 2:
The package structure combines the semiconductor die with an encapsulant material to create a composite structure that leverages the strength and protective properties of the encapsulant while maintaining the electrical and functional properties of the die
2Reliability
If encapsulant is added to protect the die, then die robustness is improved, but the package size increases beyond chip scale
Solution Approach 1:
The encapsulant is applied selectively to specific regions of the die backside, providing protection only where needed rather than uniformly across the entire package, thereby minimizing volume increase while ensuring robustness
3Reliability
If traditional packaging methods are used with encapsulant, then die robustness is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The encapsulant is applied to the die backside before the die are singulated from the wafer, allowing the encapsulation process to be integrated into the existing wafer-level manufacturing flow and avoiding additional post-singulation processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The encapsulant reduces the brittleness of the singulated dies, improving their robustness and reliability during handling and mounting, while also matching the coefficient of thermal expansion with the printed circuit board for better solder joint reliability.
Implementation Method 1
each singulated die includes an encapsulant material on the backside of the die, opposite the active surface. This encapsulant material allows the singulated die to be a composite structure which is less prone to breakage
Implementation Method 2
matching the coefficient of thermal expansion with the printed circuit board for better solder joint reliability
Data Source
AI summary
A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.