Conductive Vias in WLCSP Interconnect Structures
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Solution Overview
Problem
Current methods for forming conductive vias in semiconductor devices, such as through silicon vias, are costly and time-consuming, particularly in the context of wafer level chip scale packages (WLCSP), where efficient vertical interconnect structures are necessary for device stacking and integration.
Innovation Solution
A method involving the formation of a semiconductor die with a first interconnect structure, a protective layer, and a via through both structures, followed by the removal of the protective layer and the deposition of a conductive layer within the via, allowing for efficient and cost-effective creation of conductive vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If laser drilling and multiple plating processes are used to form conductive vias, then via formation reliability is improved, but manufacturing cost and time increase
Solution Approach 1:
The patent divides the via formation process into distinct stages: protective layer formation, via drilling through protective layer only, and subsequent conductive material deposition. This segmentation allows each step to be optimized independently, reducing overall process complexity and time while maintaining reliability.
Solution Approach 2:
The protective layer is formed in advance before via drilling, serving as a sacrificial mask that simplifies the drilling process. This preliminary action enables via formation without requiring complex simultaneous patterning and drilling operations, thereby improving manufacturing efficiency.
2Manufacturing precision
If laser drilling is used to form vias through interconnect structures, then via precision is improved, but manufacturing cost increases
Solution Approach 1:
The protective layer acts as an intermediary sacrificial material that simplifies via formation. By drilling through this temporary protective layer rather than directly through the interconnect structure, the process achieves precise via formation with reduced complexity and lower cost.
Solution Approach 2:
The protective layer is a temporary, disposable sacrificial material used only during via formation. This cheap, temporary structure enables precise via drilling without requiring expensive, complex permanent masking structures, thereby reducing manufacturing cost while maintaining precision.
3Adaptability or versatility
If multiple interconnect structures are stacked for vertical integration, then device functionality is improved, but process complexity increases
Solution Approach 1:
The patent segments the interconnect structure into multiple discrete layers (first interconnect structure, protective layer, second interconnect structure) that can be formed and processed independently. This segmentation simplifies the overall manufacturing process while enabling complex vertical integration and enhanced device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies and reduces the cost of forming conductive vias, enabling more efficient vertical interconnects in semiconductor devices, thereby facilitating smaller, higher-performance semiconductor packages with improved manufacturing efficiency.
Implementation Method 1
forming a first conductive layer in the via
Implementation Method 2
forming a first conductive layer in the via
Data Source
AI summary
A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.