Wafer Level Chip Scale Package Drain Connection
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Solution Overview
Problem
Conventional semiconductor packaging methods, such as epoxy or solder die attachment and wire bonding, are time-consuming and costly, especially for high current applications like power switching devices, and result in increased parasitics and reduced available space on printed circuit boards due to the need for additional assembly steps and metal clips for drain contacts.
Innovation Solution
A wafer-level chip scale package (WLCSP) process that electrically connects the drain region to the front side of the semiconductor device through conductive layers on the substrate's sidewalls, allowing for simultaneous metal deposition for source, gate, and drain connections, reducing the need for post-singulation manufacturing steps and metal clips, and enabling simpler, more cost-effective packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epoxy or solder die attachment with wire bonding is used, then reliable electrical connection is achieved, but the packaging process becomes time-consuming and costly with increased parasitics
Solution Approach 1:
The patent combines multiple separate packaging operations (die attachment, wire bonding, lead frame assembly) into a single integrated wafer-level process. The conductive layers are deposited directly on the wafer surface during wafer fabrication, eliminating the need for subsequent die attachment and wire bonding steps, thereby significantly improving productivity while maintaining electrical connection reliability
Solution Approach 2:
The conductive layers for electrical connection are formed in advance during wafer fabrication before the wafer is cut into individual devices. This preliminary action eliminates the need for post-dicing assembly operations, reducing packaging time and cost while maintaining reliable electrical connections
2Reliability
If metal clips are used for drain contacts, then electrical connection is achieved, but the footprint on printed circuit board increases
Solution Approach 1:
The patent extracts the drain contact function from separate metal clips and integrates it directly into the semiconductor device structure. The conductive layers extend from the active region through the substrate to the rear surface, providing drain connection without requiring external metal clips, thereby reducing PCB footprint while maintaining connection reliability
Solution Approach 2:
The conductive layers serve multiple functions simultaneously: they provide electrical connection for the drain, act as part of the device structure, and eliminate the need for separate mounting components. This multi-functionality reduces the overall space required on the PCB while ensuring reliable drain connection
3Ease of manufacture
If post-singulation assembly steps are performed, then individual device assembly is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
All conductive layers and electrical connections are formed in advance during wafer-level processing before the wafer is singulated into individual devices. This preliminary action simplifies post-assembly operations, as each individual device arrives at the assembly stage with all its electrical connections already formed, reducing manufacturing complexity and cost
Data Source
AI summary
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.