Wafer Level Chip Scale Package Fabrication via Partial Bump Embedding
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Solution Overview
Problem
Conventional semiconductor packages face issues with mechanical damage, moisture penetration, and warpage due to CTE mismatching between chips and substrates, as well as exposed conductive bumps prone to deformation and failure.
Innovation Solution
A method for fabricating wafer level chip scale packages involves laminating a wafer with bumps onto a mold plate with a protection film, singulating the wafer into chips, and fully encapsulating them with an encapsulant that partially embeds and exposes the bumps, eliminating the need for substrates and underfill materials, thereby providing complete protection and stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If substrates are used in conventional semiconductor packages, then mechanical support and electrical interconnection are provided, but chip warpage and reliability issues occur due to CTE mismatching between substrate and chip
Solution Approach 1:
The patent removes the substrate from the package structure entirely, extracting the source of CTE mismatching. The chip is directly encapsulated with underfill material and sealed with a lid, eliminating the substrate-chip interface that causes warpage while maintaining mechanical support through the encapsulation structure
Solution Approach 2:
The underfill material and encapsulation structure serve multiple functions simultaneously: providing mechanical support, enabling electrical interconnection through bumps, protecting against moisture, and preventing chip warpage. This multi-functional design replaces the traditional substrate's roles without requiring CTE-matched materials
2Strength
If underfill material is used to protect bumps, then mechanical protection is provided, but exposed chip surfaces still allow moisture penetration leading to failure
Solution Approach 1:
The patent merges the protection functions by extending the underfill material to completely encapsulate the chip, combining bump protection with moisture barrier functionality into a single continuous material layer, eliminating exposed surfaces
Solution Approach 2:
The underfill material forms a flexible encapsulation shell around the chip, providing both mechanical protection for bumps and a moisture barrier. The material conforms to the chip geometry while maintaining protective coverage on all exposed surfaces
3Object-affected harmful factors
If encapsulant is applied to protect chip surfaces, then mechanical protection is improved, but stress distribution becomes uneven causing chip warpage or cracks
Solution Approach 1:
The underfill material provides localized protection where needed - fully encapsulating the chip body and sides while leaving the bump regions accessible for electrical connection. This selective encapsulation protects vulnerable areas without creating stress concentration on the bumps
4Area of stationary object
If wafer level packaging is implemented without substrates, then footprint is reduced, but complete encapsulation must protect all surfaces including bumps
Solution Approach 1:
The patent combines multiple protective functions into the underfill material itself, which simultaneously provides mechanical support, electrical isolation, moisture barrier, and stress distribution. This integration eliminates the need for separate encapsulation layers and complex multi-component structures
Data Source
AI summary
A method for fabricating a plurality of wafer level chip scale packages is revealed. A bumped wafer is laminated with a mold plate with a protection film placed thereon to partially embed the bumps of the wafer into the protection film and to form an underfill gap between the wafer and the protection film. By a first sawing step, the wafer fixed by the protection film is singulated into a plurality of chips having sides between the active surface and the back surface and also a filling gap is formed between the sides. Then, an encapsulant is formed on the protection film where the encapsulant fills the underfill gap through the filling gap to completely encapsulate the chips and the non-embedded portions of the bumps. By separating the encapsulant from the protection film and a second sawing step, the mold plate and the protection film are removed, and the encapsulant is singulated into a plurality of individual wafer level chip scale packages.