WLCSP Interconnect Substrate Layout for Chip-to-Board Reliability
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Solution Overview
Problem
The reliability of wafer-level chip-scale packages (WLCSP) is challenged by the dissimilar properties between chips and boards, necessitating improved and cost-effective packaging methods.
Innovation Solution
A semiconductor package design featuring a redistribution layer (RDL) on the semiconductor die with exposed connecting elements, encapsulated by a molding compound, and a two-layer interconnect substrate with aligned and overlapping connecting elements for enhanced structural support and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If WLCSP packaging is used to reduce package size and eliminate substrate, then manufacturing cost decreases and thermal performance improves, but reliability deteriorates due to dissimilar properties between chip and board
Solution Approach 1:
The patent introduces an interconnect substrate as an intermediary component between the semiconductor die and the printed circuit board. This interconnect substrate acts as a mediator that bridges the dissimilar properties between chip and board, providing mechanical support, electrical interconnection, and thermal management. The interconnect substrate includes a core with first and second surfaces, metal layers on each surface, and plated through-holes for electrical connection, thereby resolving the reliability issue while maintaining the cost-effective WLCSP packaging approach
Solution Approach 2:
The patent employs composite material structures in the interconnect substrate, combining different materials with complementary properties. The substrate core is made of a material suitable for mechanical support, while metal layers (such as copper or aluminum) are deposited on the surfaces for electrical conductivity and thermal management. The plated through-holes use conductive materials to establish electrical pathways through the substrate. This composite approach allows the package to simultaneously achieve mechanical strength, electrical connectivity, and thermal performance, thereby improving reliability without sacrificing the cost benefits of WLCSP
2Object-affected harmful factors
If the molding compound completely covers the RDL and connecting elements, then environmental protection improves, but connectivity and alignment precision deteriorates
Solution Approach 1:
The patent applies local quality by selectively exposing certain regions of the RDL and connecting elements while providing molding compound protection in other areas. Specifically, the method involves forming a first opening in the molding compound to expose a portion of the RDL, and forming a second opening (different from the first opening) to expose a portion of the connecting elements. This localized exposure approach allows the molding compound to provide environmental protection where needed while maintaining manufacturing precision and connectivity where required
3Reliability
If multiple manufacturing steps are used to achieve proper alignment, then connectivity improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the interconnect substrate with integrated alignment features before the final assembly step. The interconnect substrate is manufactured with a core structure that includes metal layers and plated through-holes in predetermined positions, establishing the alignment framework in advance. This preliminary preparation of the substrate with built-in registration features simplifies the subsequent assembly process, as the components can be directly aligned to the pre-established features without requiring multiple complex alignment steps
Data Source
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Figure 3
AI summary
A semiconductor device (1) includes a semiconductor die (10) having an active surface (10a), an opposite surface (10b), a vertical sidewall (10s) extending between the active surface (10a) and the opposite surface (10b), and input/output, I/O, connections (101) disposed on the active surface (10a). A redistribution layer, RDL, (110) is disposed on the active surface (10a) of the semiconductor die (10). A plurality of first connecting elements (120) is disposed on the RDL (110). A molding compound (150) encapsulates the opposite surface (10b) and the vertical sidewall (10s) of the semiconductor die (10). The molding compound (150) also covers the RDL (110) and surrounds the plurality of first connecting elements (120). An interconnect substrate (20) is mounted on the plurality of first connecting elements (120) and on the molding compound (150).