WLCSP Interconnect Structure for Thermal Stress Management
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Solution Overview
Problem
Wafer Level Chip Scale Packages (WLCSPs) connections to printed circuit boards (PCBs) are susceptible to mechanical and thermal stress failures due to mismatches in the coefficient of thermal expansion (CTE) and the brittleness of low k dielectric layers, leading to unreliable connections.
Innovation Solution
The use of a collection of discrete conductive connections extending through a polymer layer, with varying quantities and arrangements to absorb mechanical and thermal stress, and a passivation layer to enhance the connection reliability, allowing for flexible and compliant interconnect structures that reduce stress effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single solder element connection is used to connect WLCSP to PCB, then the interconnection structure is simple, but the connection is susceptible to failure from mechanical and thermal stress
Solution Approach 1:
The single solder element connection is segmented into multiple discrete conductive connections (e.g., multiple conductive vias or traces) that collectively form the interconnection path. This segmentation distributes the mechanical and thermal stress across multiple independent pathways, preventing single-point failure and improving overall connection reliability while maintaining reasonable structural complexity.
2Adaptability or versatility
If low k dielectric layers are added to meet IC technology requirements, then the IC functionality is improved, but the brittleness increases and susceptibility to stress failure is exacerbated
Solution Approach 1:
The patent applies different material properties to different regions of the interconnection structure. Specifically, the polymer layer material is selected to have a coefficient of thermal expansion (CTE) that matches the solder element (e.g., both around 20 ppm/°C), creating a locally optimized stress-matching region that compensates for the brittleness of low k dielectric layers. This local quality adjustment allows the use of advanced low k dielectrics for IC functionality while protecting against stress failure in the connection region.
3Reliability
If polymer layer materials are adjusted to reduce stress effect, then the stress resistance is improved, but the material selection becomes more specific and restrictive
Solution Approach 1:
The patent changes the key parameter of the polymer layer material from a generic dielectric property to a specific CTE-matching property. By selecting polymer materials whose CTE matches the solder element (both around 20 ppm/°C), the patent creates a stress-matching interface that improves stress resistance. This parameter-based approach provides a clear selection criterion that maintains versatility across different solder and polymer combinations while achieving improved reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly increases the resistance to mechanical and thermal stress failures by distributing stress more evenly and providing a flexible connection that can absorb vibrations and thermal expansions, improving the reliability of the WLCSP-PCB interface.
Implementation Method 1
The discrete conductive connections of the collection are further arranged such that at least part of each discrete conductive connection makes contact with the connection element directly underneath the connection element
Implementation Method 2
The main source of thermal stress arises in mismatches in the coefficient of thermal expansion (CTE) between the IC and the PCB to which it is attached
Implementation Method 3
The solution significantly increases the resistance to mechanical and thermal stress failures by distributing stress more evenly and providing a flexible connection that can absorb vibrations and thermal expansions
Implementation Method 4
These solder elements are electrically connected to an IC chip on a second side of the dielectric by means of conductive traces extending through the layer
Data Source
AI summary
An electrical interconnect for connecting an IC chip to a PCB, the electrical interconnect comprising a plurality of connection elements for connection to the PCB attached to a first surface of the electrical interconnect, wherein the amount of thermal and/or mechanical stress that each solder element connection can take before failing is improved.