WLCSP Intermediate Structure for Thinner High-Density Packaging

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Solution Overview

Problem

The semiconductor industry faces limitations in reducing package thickness and increasing integration density due to constraints in solder ball joint height and pitch in package-on-package (PoP) technology, which hinders the miniaturization of electronic components and increases manufacturing costs.

Innovation Solution

A wafer level chip scale packaging (WLCSP) intermediate structure is developed, featuring a redistribution layer (RDL) on a carrier wafer with conductive elements and dielectric layers, allowing for the mounting of interposer dies and secondary components, along with a molding compound and interposer vias to reduce thickness and enhance electrical connectivity, enabling denser integration and reduced package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If package-on-package (PoP) technology is used to increase integration density, then more components can be integrated into a small area, but the package thickness cannot be reduced further due to constraints in solder ball joint height and pitch

Engineering Contradiction:
Improveintegration densityVSAvoidpackage thickness
Core Design Contradiction:
Quantity of substanceVSLength of stationary object

Solution Approach 1:

The patent introduces an intermediate structure with redistribution layers (RDLs) and conductive vias as a mediator between the interposer substrate and the final package. This intermediate structure enables thinner solder joints by redistributing electrical connections across multiple layers, allowing the package thickness to be reduced while maintaining integration density through the use of multiple conductive pathways in a compact vertical arrangement.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent transitions from a two-dimensional planar interconnection approach to a three-dimensional vertical stacking approach by implementing multiple redistribution layers (RDL1, RDL2, etc.) stacked vertically with conductive vias connecting them. This dimensional change allows electrical connections to be routed through the thickness direction, enabling reduced package thickness while maintaining high integration density through vertical space utilization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If solder ball joint height and pitch are reduced to minimize package size, then package dimensions decrease, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvepackage sizeVSAvoidmanufacturing complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent segments the interconnection structure into multiple functional layers including interposer substrate, multiple redistribution layers (RDL1, RDL2, RDL3), conductive vias, and capping layer. Each layer performs a specific function: the interposer provides mechanical support, RDLs provide electrical redistribution, vias provide vertical interconnection, and the capping layer provides protection. This segmentation allows standard manufacturing processes to be applied to each layer independently, reducing overall manufacturing complexity while achieving compact package size.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The intermediate structure with redistribution layers serves multiple functions simultaneously: it provides electrical redistribution to accommodate reduced pitch, acts as a mechanical support structure, enables vertical interconnection through vias, and allows for thermal management. This multi-functionality reduces the need for additional specialized components, thereby controlling manufacturing complexity while achieving miniaturization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If traditional PoP technology is used with standard solder ball joints, then manufacturing is simpler, but package thickness and size cannot be minimized

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidpackage thickness
Core Design Contradiction:
Ease of manufactureVSLength of stationary object

Solution Approach 1:

The patent implements preliminary actions by pre-forming the intermediate structure with multiple redistribution layers and conductive vias on the interposer substrate before mounting the semiconductor devices. The RDLs are patterned and cured in advance, and the capping layer is applied beforehand to protect the conductive structures. This preliminary preparation enables subsequent assembly steps to be simpler and more straightforward, while the pre-configured intermediate structure enables reduced package thickness through optimized vertical interconnections.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12051616B2Wafer level chip scale packaging intermediate structure apparatus and method
Publication Date: 2024.07.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12051616B2 patent drawing
  • US12051616B2 patent drawing
  • US12051616B2 patent drawing

AI summary

Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.