Wafer-Level Chip Scale Package With Liquid Molding Compound

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing the physical size of semiconductor devices while maintaining reliability and efficiency, particularly in the packaging of semiconductor dies, where existing techniques are limited by the need for smaller and more creative packaging methods.

Innovation Solution

The implementation of a wafer-level chip scale package structure with a liquid molding compound layer that protects the semiconductor device from heat, shock, and corrosion, and reduces mechanical and thermal stresses, while also simplifying the fabrication process by direct bonding of bumps to metal lines, thereby reducing the number of mask layers required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If wafer-level chip scale package structure is implemented, then device size is reduced and integration density is improved, but fabrication complexity increases due to multiple metallization layers and patterning steps

Engineering Contradiction:

Improvedevice sizeVSAvoidfabrication complexity

Core Design Contradiction:

Volume of moving objectVSDevice complexity

Solution Approach 1:

The fabrication process is divided into separate wafer-level processing steps for different functional layers (interconnect, passivation, polymer, metallization). Each layer is formed and patterned independently on the wafer before final assembly, allowing parallel processing and reducing overall fabrication complexity while maintaining small device size.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from traditional chip-scale packaging to wafer-level packaging, adding a vertical dimension to the fabrication process. Multiple metallization layers are stacked in three-dimensional space, enabling higher integration density without increasing the horizontal footprint of the device.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple metallization layers and patterning steps are used, then interconnect functionality is improved, but manufacturing time and cost increase

Engineering Contradiction:

Improveinterconnect functionalityVSAvoidmanufacturing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Multiple metallization layers, passivation layers, and polymer layers are formed in advance on the wafer substrate before the final packaging assembly. Seed layers are deposited and patterned beforehand, allowing subsequent plating and assembly steps to proceed quickly without repeated processing cycles.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent combines multiple fabrication operations into integrated process steps. For example, seed layer formation is combined with subsequent metal plating, and passivation layer formation is combined with polymer layer deposition. This merging of steps reduces the total number of discrete manufacturing operations while maintaining interconnect functionality.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If traditional packaging techniques are used, then fabrication process is simpler, but device size reduction is limited

Engineering Contradiction:

Improvefabrication process simplicityVSAvoiddevice size

Core Design Contradiction:

Ease of manufactureVSVolume of moving object

Solution Approach 1:

The patent replaces traditional mechanical packaging techniques with wafer-level semiconductor fabrication processes. Instead of assembling discrete chips into packages, the entire package structure is formed directly on the wafer using deposition, etching, and plating processes, enabling continuous scaling to smaller dimensions while maintaining manufacturing simplicity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Object-affected harmful factors

If more packaging layers are added for protection, then environmental protection is improved, but mechanical stress on the device increases

Engineering Contradiction:

Improveenvironmental protectionVSAvoidmechanical stress

Core Design Contradiction:

Object-affected harmful factorsVSStress or pressure

Solution Approach 1:

The patent modifies the physical and chemical parameters of the packaging layers. The polymer layer is formulated with specific mechanical properties to provide environmental protection while accommodating thermal expansion. The passivation layer thickness and composition are optimized to protect against corrosion without creating excessive mechanical stress on the underlying interconnect structures.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9437564B2Interconnect structure and method of fabricating same

Publication Date: 2016.09.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer formed over the passivation layer, wherein the redistribution layer is connected to the connection pad, a bump formed over the redistribution layer, wherein the bump is connected to the redistribution layer and a molding compound layer formed over the redistribution layer. The molding compound layer comprises a flat portion, wherein a bottom portion of the bump is embedded in the flat portion of the molding compound layer and a protruding portion, wherein a middle portion of the bump is surrounded by the protruding portion of the molding compound layer.