Wafer Level Chip Scale Package Interconnect Structure

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Solution Overview

Problem

Existing interconnect technologies in semiconductor devices face challenges in achieving reliable connections between substrates while minimizing mechanical failures and parasitic capacitance, particularly in wafer level chip scale packages (WLCSPs), due to limitations in layer thickness and alignment.

Innovation Solution

The implementation of a conductive post-passivation interconnect (PPI) structure, which includes a passivation layer, an insulation layer, a conductive PPI layer extending over the insulation layer without intervening insulation between the PPI and the land, and a protective layer, allowing for thicker overlying layers and customized interconnect layouts without increasing device thickness, thereby enhancing reliability and reducing mechanical failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional interconnect structures with multiple insulation layers are used, then alignment precision can be improved, but device thickness increases and manufacturing complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoiddevice thickness
Core Design Contradiction:
Manufacturing precisionVSLength of stationary object

Solution Approach 1:

The patent removes the intermediate insulation layer between the conductive PPI layer and the land, extracting only the essential insulation function while eliminating unnecessary thickness. The conductive PPI layer is deposited directly on the land surface, with insulation provided only where needed (under the protective layer and in non-contact regions), thereby achieving precise alignment without increasing overall device thickness.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies insulation properties locally rather than uniformly throughout the interconnect structure. The insulation layer is present only in regions where electrical isolation is required, while the conductive PPI layer maintains direct contact with the land in contact regions. This localized approach provides necessary alignment precision while minimizing unnecessary thickness accumulation.

Inventive Principle:
Principle #3Local quality

2Reliability

If thicker overlying layers are used to enhance reliability, then interconnect strength is improved, but device thickness increases

Engineering Contradiction:
Improveinterconnect strengthVSAvoiddevice thickness
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent shifts the thickness enhancement from the vertical dimension to the lateral dimension. The conductive PPI layer is extended laterally beyond the land boundaries, allowing thicker and more reliable interconnect structures in the horizontal plane while maintaining a thin vertical profile. This enables robust mechanical connections without increasing the overall device thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interconnect structure is segmented into functional regions: a contact region where the conductive PPI layer directly touches the land for electrical connection, and extended regions where the conductive layer provides mechanical strength and customization. This segmentation allows the thick conductive layer to provide reliability where needed while keeping the overall structure thin through strategic placement.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If customized interconnect layouts are implemented using metal lines in dielectric, then layout flexibility is improved, but device thickness and manufacturing complexity increase

Engineering Contradiction:
Improvelayout flexibilityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent changes the fundamental parameter of interconnect formation from embedded metal lines within multiple dielectric layers to a direct deposition approach. The conductive PPI layer is deposited directly on the land surface, allowing layout customization through patterned deposition without requiring complex multi-layer dielectric stacking. This simplifies manufacturing while maintaining layout flexibility.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9281234B2WLCSP interconnect apparatus and method
Publication Date: 2016.03.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9281234B2 patent drawing
  • US9281234B2 patent drawing
  • US9281234B2 patent drawing

AI summary

Disclosed herein is an interconnect apparatus comprising a substrate having a land disposed thereon and a passivation layer disposed over the substrate and over a portion of the land. An insulation layer is disposed over the substrate and has an opening disposed over at least a portion of the land. A conductive layer is disposed over a portion of the passivation layer and in electrical contact with the land. The conductive layer has a portion extending over at least a portion of the insulation layer. The conductive layer comprises a contact portion disposed over at least a portion of the land. The insulation layer avoids extending between the land and the contact portion. A protective layer may be disposed over at least a portion of the conductive layer and may optionally have a thickness of at least 7 μm.