Wafer Level Chip Scale Packaging Peripheral Removal

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Solution Overview

Problem

The peripheral portions of wafers are susceptible to damage during the molding and dicing processes in existing wafer level chip scale packaging methods, leading to issues in molding quality and production yield.

Innovation Solution

The method involves dicing the wafer into independent bottom chips and removing the peripheral portions before molding, allowing the molding compound to completely enclose the bottom chips and preventing damage from external forces, with a carrier bonded to the wafer to distribute clamping stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If annular clamps are used to secure the wafer during molding, then the wafer can be held firmly in place, but the peripheral portions of the wafer are easily crushed or damaged

Engineering Contradiction:
Improvewafer securing reliabilityVSAvoidperipheral portion damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the wafer processing by removing peripheral portions that are susceptible to damage before the molding process. This segmentation separates the vulnerable peripheral areas from the main chip areas, allowing the annular clamps to secure the wafer without causing damage to critical regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by removing the peripheral portions of the wafer before the molding process begins. This pre-removal prevents the peripheral portions from being subjected to crushing forces during molding, while still allowing the annular clamps to effectively secure the remaining wafer structure.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the wafer is molded before dicing, then the molding compound can cover the entire wafer surface, but the peripheral portions are susceptible to damage during the process

Engineering Contradiction:
Improvemolding compound coverageVSAvoidperipheral portion damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent inverts the conventional sequence by removing peripheral portions before molding rather than molding the complete wafer first. This reversal allows the molding compound to cover only the necessary chip areas without exposing peripheral portions to damage risks during the molding process.

Inventive Principle:
Principle #13The other way round (Inversion)

3Reliability

If annular clamps press the peripheral portions to secure the wafer, then the wafer is firmly held, but chips at peripheral portions of neighboring wafers are affected

Engineering Contradiction:
Improvewafer clamping effectivenessVSAvoidmolding quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts or removes the peripheral portions of the wafer before the molding process. This extraction eliminates the source of the problem where annular clamps would otherwise press on and damage peripheral portions, thereby preventing adverse effects on chips at peripheral portions of neighboring wafers while maintaining effective wafer clamping.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the packaging quality and production yield of the WLCSP structure by preventing chip damage during the molding process and ensuring consistent molding compound coverage.

Implementation Method 1

a molding compound may initially be in a liquid state (or be heated to a liquid state), and the molding compound then may be cured through a cooling process

Methodology Applied
Scientific EffectCooling: Cooling

Data Source

PatentEP3888122B1Chip molding structure, wafer level chip scale packaging structure and manufacturing method thereof
Publication Date: 2023.06.07 CHANGXIN MEMORY TECH INC
  • EP3888122B1 patent drawingFigure 1~3
  • EP3888122B1 patent drawingFigure 4
  • EP3888122B1 patent drawingFigure 5

AI summary

A chip molding structure, a wafer level chip scale packaging structure and manufacturing methods thereof are disclosed, relating to the technical field of semiconductor production. The method of making a wafer level chip scale packaging structure includes: providing a wafer, comprising a plurality of bottom chips; bonding the wafer with a carrier; dicing the wafer to separate the plurality of bottom chips from a plurality of peripheral portions; removing the plurality of peripheral portions; and molding the plurality of bottom chips with a mold to form the molding structure. By dicing the wafer into independent bottom chips and peripheral portions, with the peripheral portions being removed before molding, the bottom chips may be prevented from being damaged during the molding. Compared with existing technologies, the packaging quality and production yield are improved.