Wafer-Level Chip Packaging Protective Layer for Electroplating
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Solution Overview
Problem
Current Wafer-level-chip-size-packaging (WLCSP) methods face issues with metal precipitation during electroplating, leading to short circuit failures and exposure of chip sidewalls, which can result in damage and reduced yield due to the electroplating process and subsequent packaging processes.
Innovation Solution
A method involving the formation of a first protective layer in the slicing trails using thermosetting epoxy resin, which prevents metal separation during electroplating and protects the sidewalls of individual chips, combined with sub-ball metal electrodes formed using electrolyte-less plating or selective vapor deposition, and a second protective layer to enhance protection and packaging efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electroplating process is used to form external leads, then electrical connection is achieved, but metal precipitation occurs in slicing trails causing short circuit failures
Solution Approach 1:
The patent applies preliminary action by forming the first protective layer in the slicing trails before the electroplating process. This protective layer prevents metal precipitation during electroplating by blocking the electroplating solution from contacting the slicing trail regions, thereby preventing short circuit failures while still allowing electrical connection to be formed on the bonding pads.
Solution Approach 2:
The first protective layer acts as an intermediary substance between the electroplating solution and the slicing trails. It selectively allows the electroplating process to proceed on the bonding pads while preventing metal deposition in the slicing trails, thus mediating between the need for electrical connection and the need to prevent short circuits.
2Ease of manufacture
If slicing trails are exposed during packaging, then chip separation is enabled, but sidewalls of chips are exposed to outer environment causing damage and reduced yield
Solution Approach 1:
The patent applies preliminary action by forming the first protective layer in the slicing trails before the chip separation and packaging processes. This protective layer remains after slicing, providing continuous protection to the sidewalls of separated chips during subsequent packaging operations, preventing environmental damage while maintaining chip separation capability.
Solution Approach 2:
The first protective layer functions as a thin film that conforms to the sidewalls of chips after slicing. This flexible protective film follows the chip geometry and provides continuous protection during packaging, preventing mechanical damage and environmental contamination without interfering with chip separation.
3Volume of moving object
If conventional WLCSP packaging is used, then miniaturization is achieved, but metal damage and short circuits occur during electroplating and packaging
Solution Approach 1:
The patent applies preliminary action by pre-forming the first protective layer in the slicing trails before electroplating and packaging operations. This protective layer remains in place during miniaturized chip processing, preventing metal wire damage and short circuits while enabling the continued miniaturization of chip size through WLCSP packaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents metal damage and increases packaging efficiency and yield by protecting the sidewalls and metal wires, reducing the risk of short circuits and chip damage during packaging.
Implementation Method 1
During the formation of the external leads 12 using the electroplating process, metal may be precipitated from the slicing trails
Implementation Method 2
forming a first protective layer in the slicing trails using thermosetting epoxy resin
Implementation Method 3
sub-ball metal electrodes formed using electrolyte-less plating or selective vapor deposition
Implementation Method 4
sub-ball metal electrodes formed using electrolyte-less plating or selective vapor deposition
Data Source
AI summary
Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming a first protective layer on the cutting trail; forming on the metal bonding pad a sub-ball metal electrode; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The first protective layer according to the present invention can prevent the metal in the cutting trail from being separated by electroplating, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.