Wafer-Level Chip Package Redistribution Layer Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional wafer-level chip-size packages (WLCSPs) have a large footprint due to the step-height of the first planarization layer, which restricts the size of the bonding pad and prevents the integration of additional conductive components, hindering the miniaturization of integrated circuits.
Innovation Solution
A method is developed to form a WLCSP with an additional conductive component adjacent to the bonding pad, isolated by a trench and integrated using a series of planarization and patterning steps, allowing for a more compact design with reduced bonding pad size and enabling multiple electrical potentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a first planarization layer is formed over the passivation layer to planarize the surface, then the surface flatness is improved, but the footprint area increases due to step-height
Solution Approach 1:
The patent introduces a second planarization layer formed over the first planarization layer, transitioning from a single-layer planarization approach to a multi-layer planarization structure. This dimensional addition in the vertical stacking direction allows the bonding pad opening to be positioned at an optimal height, reducing the horizontal footprint while maintaining surface flatness for bump formation.
2Area of stationary object
If the bonding pad size is reduced to minimize footprint, then the footprint area is improved, but the electrical connection reliability deteriorates
Solution Approach 1:
The patent utilizes vertical positioning of the bonding pad opening through the multi-layer planarization structure to maintain adequate electrical connection area while reducing the overall footprint. The opening can be positioned at a height where it maintains reliable electrical connection without requiring excessive horizontal area.
Solution Approach 2:
The patent changes the vertical position parameter of the bonding pad opening relative to the planarization layers, allowing optimization of both the footprint area and electrical connection reliability by controlling where the opening intersects the conductive structures beneath.
3Adaptability or versatility
If additional conductive components are integrated adjacent to the bonding pad, then the functionality is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the planarization structure into multiple layers, allowing different regions (bonding pad area and adjacent conductive component areas) to be independently defined and formed. This segmentation enables the integration of multiple functional elements while maintaining a systematic manufacturing process.
Solution Approach 2:
The multi-layer planarization structure serves multiple functions simultaneously: it provides surface flatness for bump formation, defines the bonding pad opening position, and enables the integration of additional conductive components. This universal structure handles both planarization and component integration without requiring separate dedicated structures.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.