Wafer-Level Chip-Scale Package Redistribution Layer Planarization
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Solution Overview
Problem
Wafer-level chip scale packages (WLCSPs) face challenges in reducing size due to large step-heights in the redistribution layer and UBM layer formation, leading to increased footprint and manufacturing complexity.
Innovation Solution
A method involving a single planarization layer with controlled thickness and patterning to expose bonding pads, followed by a conformable conductive redistribution layer and UBM layer formation, allowing for a flat surface for bump formation, reducing the size and complexity of the WLCSP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple planarization layers are used to achieve a flat surface for bump formation, then the surface flatness is improved, but the manufacturing complexity and process steps increase
Solution Approach 1:
The patent extracts and eliminates the second planarization layer from the conventional multi-layer structure, retaining only the first planarization layer. This simplification is achieved by optimizing the conformable redistribution layer to provide sufficient flatness for bump formation without requiring additional planarization steps, thereby reducing manufacturing complexity while maintaining surface flatness requirements
Solution Approach 2:
The patent merges the functions of multiple planarization layers into a single planarization layer combined with a conformable redistributive conductive layer. The conformable redistributive conductive layer is formed to be substantially coplanar with the passivation layer, effectively combining the planarization and redistribution functions into an integrated structure that reduces the total number of process steps
2Strength
If large step-heights are present in redistribution layer and UBM layer formation, then the structural integrity is maintained, but the footprint size increases
Solution Approach 1:
The patent transitions from a vertical stacking approach with large step-heights to a substantially coplanar arrangement where the conformable redistributive conductive layer is formed at substantially the same elevation as the passivation layer. This dimensional reorganization eliminates the need for large vertical steps while maintaining all necessary structural connections, thereby reducing the horizontal footprint size
Solution Approach 2:
The patent changes the geometric parameters of the redistribution layer by forming it with controlled thickness and elevation to be substantially coplanar with the passivation layer. This parameter optimization allows the UBM layer and bumps to be formed in a much smaller vertical space, reducing the overall footprint while maintaining structural integrity through precise dimensional control
Data Source
AI summary
A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer.