Wafer-Level Chip Scale Packaging with Rewiring Layer
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Solution Overview
Problem
Current wafer-level chip scale packaging technologies face challenges in integrating multiple chips into a single packaging structure, leading to increased area size, instability, and yield loss due to in-plane warpage issues, which affects chip performance and production costs.
Innovation Solution
A method involving a first and second packaging layer with a rewiring layer electrically connected to chips, where the first packaging layer is peeled off from a supporting substrate and attached to another substrate, with a second packaging layer covering the first chips and a rewiring layer formed above, allowing for the integration of multiple chips and mitigating warpage defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are packaged in the same packaging structure using current WLCSP technologies, then the packaging area size increases significantly, but the in-plane warpage increases causing instability and yield loss
Solution Approach 1:
The patent divides the packaging structure into multiple independent packaging cavities, each capable of holding one or more chips. This segmentation allows multiple chips to be packaged while maintaining stable in-plane characteristics in each cavity, preventing warpage-induced instability and yield loss.
Solution Approach 2:
The patent introduces a vertical dimension by stacking multiple packaging layers (first packaging layer, second packaging layer, third packaging layer) with through-holes connecting them. This multi-layer structure enables packaging multiple chips in the same footprint area while maintaining warpage control through the distributed vertical architecture.
2Quantity of substance
If multiple chips are packaged in the same packaging structure, then more chips are integrated, but the packaging structure area increases
Solution Approach 1:
The patent utilizes vertical stacking with multiple packaging layers connected by through-holes to achieve three-dimensional integration. This allows multiple chips to be packaged within the same planar footprint by distributing them across different vertical levels, effectively increasing integration density without expanding the packaging structure's footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple packaging layers are contained within a single packaging structure, with through-holes providing vertical connectivity. This nesting approach enables compact integration of multiple chips in a space-efficient manner.
3Quantity of substance
If current WLCSP packaging processes are used for multiple chips, then packaging is achieved, but the process is difficult to integrate into existing processes causing instability
Solution Approach 1:
The patent segments the packaging process into standardized steps (forming multiple packaging cavities, placing chips in each cavity, forming through-holes, filling with conductive material) that can be integrated into existing WLCSP production lines. Each step uses conventional semiconductor manufacturing techniques, ensuring ease of integration while achieving multi-chip packaging.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the multi-layer packaging structure with through-holes before final chip placement and connection. This preliminary structuring simplifies subsequent assembly steps and enables better integration with existing processes by establishing a ready-made framework for chip integration.
4Productivity
If in-plane warpage is not controlled within specified range, then packaging is completed, but products deform under stress affecting yield
Solution Approach 1:
By dividing the packaging structure into multiple independent cavities and layers, the patent distributes mechanical stress across segmented regions. This segmentation prevents stress concentration that would cause deformation, maintaining reliability while completing packaging of multiple chips.
Solution Approach 2:
The patent applies local quality by providing specific structural features (through-holes with conductive filling, support structures) at critical locations within the packaging structure. These localized features reinforce stress-prone areas and control warpage in specific regions, preventing deformation while maintaining overall packaging functionality.
Data Source
AI summary
The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer.