Wafer-Level Chip Scale Package Side Protection
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Solution Overview
Problem
Wafer-Level Chip Scale Packages (WLCSP) are susceptible to mechanical damage due to lack of protection on lateral side walls and front sides, which can lead to chipping and compromise the device.
Innovation Solution
A semiconductor device with a device die having a top surface, bottom surface, and sidewalls, where a first protective layer covers the top surface and sidewalls with varying thicknesses, and a second protective layer covers the bottom surface, providing overall protection. The method involves cutting the device die with stepped edges and applying protective layers to prevent damage from side strikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If molding material is deposited only on the backside of the wafer, then the backside of the die is protected, but the lateral side walls and front side remain susceptible to mechanical damage such as chipping
Solution Approach 1:
The protective coverage is extended from a single dimension (backside only) to multiple dimensions by forming protective layers that cover the lateral side walls and front side in addition to the backside, creating comprehensive three-dimensional protection against mechanical damage
Solution Approach 2:
Different regions of the die receive differentiated protective treatment: the backside receives molding material, while the lateral side walls and front side receive additional protective layers, with each region's protection tailored to its specific mechanical stress requirements
2Reliability
If the protective layer thickness is uniform across the sidewall, then manufacturing is simpler, but the top surface area requiring protection is insufficiently covered
Solution Approach 1:
The protective layer is designed with asymmetric thickness distribution along the sidewall, being thicker at the top portion and thinner at the bottom portion, optimizing protection for the top surface area while maintaining manufacturability
Solution Approach 2:
The protective layer thickness is locally optimized according to the specific protection needs of different sidewall regions, with greater thickness at the top where more protection is required and reduced thickness at the bottom where less protection is needed
Data Source
AI summary
A semiconductor device includes a device die having a top surface, a bottom surface, and sidewalls between the top and bottom surfaces. A first protective layer covers at least the top surface and the sidewalls of the die. A thickness of the first protective layer on the sidewalls near the top surface is greater than a thickness of the first protective layer on the sidewalls die near the bottom surface.