WLCSP Bandwidth Extension via Optimized Solder Ball Parameters

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Solution Overview

Problem

Conventional wafer level chip scale packaging (WLCSP) for millimeter-wave circuits faces challenges with bandwidth limitations, high manufacturing costs, and performance inconsistencies due to large ball diameters or small ball sizes, which affect cost-effectiveness and wafer test yield.

Innovation Solution

The design incorporates optimized solder ball sizes (120-180 um diameter and 100-150 um height) with corresponding chip pad and passivation opening sizes, utilizing a 400 um pitch and compatible PCB pad and solder mask opening sizes, along with an edge solder ball path for signal and five surrounding ball paths as ground, to extend bandwidth beyond 100 GHz while maintaining low costs and ensuring consistent performance with or without PCB pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If standard conventional WLCSP uses relatively large ball diameters (approximately 250 um) for cost effectiveness, then manufacturing cost is reduced, but bandwidth is limited to approximately 70 GHz

Engineering Contradiction:
Improvemanufacturing costVSAvoidbandwidth
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent changes the ball diameter parameter from conventional large sizes (250 um) to optimized medium sizes (120-180 um), and adjusts corresponding parameters including ball height (100-150 um), pitch (400 um), PCB pad sizes, and solder mask opening sizes to achieve both cost-effectiveness and extended bandwidth beyond 100 GHz

Inventive Principle:
Principle #35Parameter changes

2Speed

If specialized conventional WLCSP designs use relatively small ball diameters (30-100 um) to extend bandwidth to approximately 100 GHz, then bandwidth is improved, but manufacturing costs increase and wafer test yield decreases

Engineering Contradiction:
ImprovebandwidthVSAvoidmanufacturing cost
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The patent optimizes the ball diameter to a medium range (120-180 um) that avoids the high cost of small balls (30-100 um) while still achieving bandwidth beyond 100 GHz, and sets corresponding pitch (400 um) and height (100-150 um) parameters to maintain manufacturing ease and wafer test yield

Inventive Principle:
Principle #35Parameter changes

3Speed

If specialized conventional WLCSP designs use small ball diameters (30-100 um), then bandwidth is extended, but wafer test yield decreases due to performance inconsistency between designs utilizing and not utilizing PCB pads

Engineering Contradiction:
ImprovebandwidthVSAvoidwafer test yield
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent uses optimized medium ball diameters (120-180 um) with corresponding pitch (400 um) and height (100-150 um) parameters that provide consistent performance whether PCB pads are utilized or not, thereby extending bandwidth beyond 100 GHz while maintaining high wafer test yield

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent designs a universal WLCSP configuration with optimized parameters that performs consistently in both scenarios (with and without PCB pads), making the design adaptable and reliable for different application requirements while achieving bandwidth beyond 100 GHz

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9236361B2Millimeter wave wafer level chip scale packaging (WLCSP) device
Publication Date: 2016.01.12 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9236361B2 patent drawing
  • US9236361B2 patent drawing
  • US9236361B2 patent drawing

AI summary

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.