Compliant Stress Relief Buffer for Large Array WLCSP Warpage
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Solution Overview
Problem
Large array WLCSP and FO-WLCSP semiconductor devices experience reliability issues such as solder joint failures during temperature cycling and warpage due to their large die size, which affects their performance and integration.
Innovation Solution
A compliant stress relief buffer made of materials like polymers or epoxy resin with fillers is disposed around or adjacent to the semiconductor die, along with an encapsulant, to absorb thermo-mechanical stress and reduce warpage, thereby enhancing the reliability of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If large array WLCSP and FO-WLCSP semiconductor devices are manufactured with large die size to achieve higher functional integration, then functional integration is improved, but solder joint reliability deteriorates during temperature cycling and drop impact testing
Solution Approach 1:
A stress relief buffer layer is introduced as an intermediary component between the large array WLCSP die and the substrate. This buffer layer absorbs thermo-mechanical stress and prevents direct transmission to the solder joints, thereby maintaining solder joint reliability while allowing the use of large die sizes for higher functional integration.
Solution Approach 2:
The stress relief buffer layer modifies the mechanical properties of the package structure by introducing a layer with specific compliance characteristics. This changes the stress distribution parameters within the package, reducing peak stresses at critical locations such as solder joints during temperature cycling and mechanical impact.
2Adaptability or versatility
If large array WLCSP and FO-WLCSP semiconductor devices are manufactured with large die size to achieve higher functional integration, then functional integration is improved, but warpage increases
Solution Approach 1:
The stress relief buffer layer acts as a mediator that compensates for warpage in large array WLCSP devices. By positioning this compliant layer strategically within the package structure, it counteracts the warping forces generated by large die sizes, maintaining planarity while enabling higher functional integration.
3Reliability
If stress relief buffer is added around semiconductor die to absorb thermo-mechanical stress, then solder joint reliability is improved, but device complexity increases
Solution Approach 1:
The stress relief buffer layer is implemented as a segmented or localized feature rather than a complete wraparound structure. This segmentation approach provides the necessary stress relief functionality while minimizing the added complexity and material usage, making the package structure more manufacturable.
4Shape
If compliant material buffer is disposed around semiconductor die, then warpage is reduced, but manufacturing complexity increases
Solution Approach 1:
The compliant material buffer is applied as a segmented or partial structure rather than a complete surround. This segmentation reduces the complexity of the manufacturing process while still achieving the warpage reduction effect in critical areas of the large array WLCSP package.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compliant stress relief buffer effectively reduces solder joint failures and warpage, improving the reliability and integration of large array WLCSP and FO-WLCSP semiconductor devices by absorbing thermo-mechanical stress and maintaining package integrity during temperature cycling and mechanical shocks.
Implementation Method 1
A need exists to reduce solder joint failure in large array WLCSP and FO-WLCSP. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the step of providing a semiconductor die or component including an electrical functionality and a mechanical functionality, disposing a stress relief buffer including a compliant material around the semiconductor die or component
Data Source
AI summary
A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.