Wafer Level Packaging Alignment Marks for Dicing Accuracy
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Solution Overview
Problem
Conventional wafer level packaging technologies face challenges in achieving accurate die separation during the dicing process due to the encapsulation material covering scribe lines, which reduces die sawing accuracy.
Innovation Solution
Incorporation of alignment marks between bond pads and guard rings at various layers, including the post-passivation interconnect layer, to enhance the accuracy of the dicing process by providing visible reference points for die separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encapsulation material is used to cover scribe lines in WLP technology, then device protection and integration are improved, but die sawing accuracy deteriorates
Solution Approach 1:
Alignment marks are formed on the wafer before the encapsulation process. These marks are positioned at predetermined locations that will remain accessible or detectable after encapsulation, allowing the dicing saw to accurately locate and follow scribe lines despite the encapsulation material coverage.
Solution Approach 2:
Alignment marks serve as intermediary reference features between the encapsulation structure and the dicing process. These marks provide a visible or detectable interface that allows the dicing system to accurately locate scribe lines without directly viewing the scribe lines themselves, which are obscured by encapsulation material.
2Manufacturing precision
If alignment marks are added to improve dicing accuracy, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The alignment mark system is segmented into discrete, simple geometric features (such as notches, holes, or metal patterns) that are distributed at specific locations around the die periphery. This segmentation allows each mark to be independently formed using existing fabrication processes without requiring a complete redesign of the device structure.
Solution Approach 2:
Alignment marks are placed only at specific critical locations (such as corners or edges of the die) rather than uniformly across the entire device. This localized approach provides the necessary reference information for dicing accuracy while minimizing the addition of structural elements and maintaining overall device simplicity.
Data Source
AI summary
A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.