Wafer Level Package 3D Stacking via Bonding Wire Segmentation
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Solution Overview
Problem
Current wafer level packaging technologies face challenges in achieving 3D stacking due to high manufacturing costs and structural weaknesses, particularly in fan-out wafer level packages, which lack sufficient structural strength and are prone to warpage from thermal expansion coefficient differences.
Innovation Solution
A semiconductor package structure featuring a die, bonding wires, an encapsulant, and external connection terminals, where the bonding wires are partially exposed and connected to the encapsulant, allowing for vertical electrical conduction and enabling 3D stacking with improved structural integrity through a simplified process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fan-out wafer level package structure is used, then packaging process is simplified and cost is reduced, but structural strength is insufficient and warpage occurs
Solution Approach 1:
The patent employs a composite structure combining encapsulant material with a reinforcement layer (such as metal foil or rigid substrate) to create a package structure that maintains the simplicity of fan-out wafer level packaging while significantly enhancing structural strength and dimensional stability to prevent warpage
2Ease of manufacture
If fan-out wafer level package structure is used, then packaging process is simplified and cost is reduced, but package reliability is compromised due to warpage
Solution Approach 1:
By integrating a reinforcement layer with the encapsulant, the composite package structure maintains manufacturing simplicity while ensuring dimensional stability and preventing warpage, thereby preserving or enhancing package reliability
Solution Approach 2:
The patent modifies the physical and mechanical parameters of the package structure by introducing materials with different thermal expansion coefficients and mechanical properties, balancing the thermal stress and preventing warpage that would compromise reliability
3Adaptability or versatility
If through-silicon-via structure is used for 3D stacking, then vertical electrical conduction is achieved, but manufacturing cost and difficulty increase significantly
Solution Approach 1:
The patent divides the electrical conduction path into separate segments: bonding wires provide vertical electrical connection between stacked packages, while the reinforcement layer provides structural support. This segmentation avoids the need for complex through-silicon-via fabrication while achieving 3D stacking functionality
Solution Approach 2:
The patent introduces bonding wires as an intermediary element that establishes electrical connections between stacked packages without requiring direct penetration through the substrate, thereby simplifying the manufacturing process while enabling vertical electrical conduction
Data Source
AI summary
The present invention provides a method for manufacturing a semiconductor package structure, including (i) providing a carrier plate; (ii) disposing a die on the carrier plate; (iii) forming a plurality of bonding wires having a first end and a second end; (iv) forming an encapsulant covering the die and the bonding wires and exposing a portion of each of the bonding wires from a first surface thereof; (v) removing the carrier plate; (vi) forming a patterned conductive layer on a second surface of the encapsulant opposite to the first surface; (vii) electrically connecting the second ends of the bonding wires to the active surface of the die via the patterned conductive layer; and (viii) forming a plurality of first external connection terminals on the first surface of the encapsulant respectively covering the portions of the bonding wires exposed from the encapsulant.