Wafer-Level Package Copper Pillars High-Current Interconnect
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Solution Overview
Problem
Flat no-lead packaging technologies, such as QFN, are expensive and provide relatively low pin counts, whereas wafer-level packaging is less costly and offers smaller package sizes but lacks mechanical protection similar to QFN devices.
Innovation Solution
The development of wafer-level package semiconductor devices with copper pillars and an encapsulation structure that provide electrical interconnectivity and mechanical protection, allowing for high-current applications while maintaining the cost and size benefits of wafer-level packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wafer-level packaging is used, then manufacturing cost is reduced and package size is minimized, but mechanical protection is insufficient
Solution Approach 1:
The patent embeds multiple functional elements within the wafer-level package structure: copper pillars are integrated into the substrate, encapsulation material surrounds and protects the pillars, and solder contacts are formed on the pillar surfaces. This nested arrangement provides mechanical protection while maintaining the compact wafer-level form factor and cost benefits.
Solution Approach 2:
The patent employs composite material structures combining different materials with complementary properties: copper pillars provide electrical conductivity and mechanical strength, encapsulation material (such as epoxy or polymer) provides mechanical protection and environmental sealing, and solder material provides reliable electrical and mechanical connections. This composite approach resolves the contradiction between cost-effectiveness and mechanical protection.
2Volume of moving object
If wafer-level packaging is used, then package size is minimized, but pin count is limited
Solution Approach 1:
The patent transitions from planar two-dimensional contact structures to three-dimensional vertical structures by forming copper pillars that extend upward from the substrate surface. This dimensional change allows multiple solder contacts to be arranged on the vertical pillar surfaces, significantly increasing the effective pin count within the same footprint area while maintaining compact package size.
3Reliability
If copper pillars with encapsulation structure are added, then mechanical protection and electrical connectivity are enhanced, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into integrated structures: the copper pillars simultaneously provide electrical interconnectivity, mechanical support, and structural framework for solder contacts. The encapsulation material simultaneously protects the pillars mechanically, provides environmental sealing, and enables proper solder contact formation. This functional integration enhances reliability while minimizing the increase in device complexity.
Data Source
AI summary
Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.