Wafer Level Package Integrated Antenna Shielding
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Solution Overview
Problem
Conventional wafer level package systems with integrated antennas face signal integrity issues due to long signal paths and undesired radiation, which limit their performance in high-frequency wireless systems, and lack design freedom and EMC shielding.
Innovation Solution
A wafer level package design with an integrated antenna that eliminates the redistribution layer, featuring a chip layer, dielectric layer with through-connections, and an antenna layer, where a shield is integrated in the contacting layer to decouple the antenna from the chip and other components, allowing direct connection and improved radiation behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If antennas are integrated on the interposer or printed circuit board, then antenna efficiency and gain are improved, but signal path length increases causing signal integrity problems
Solution Approach 1:
The patent transitions from planar antenna integration on the same layer as the chip to a three-dimensional stacked architecture. The antenna is positioned in a separate antenna layer above the chip layer, connected through vertical via connections. This vertical stacking enables short signal paths while providing spatial separation between the chip and antenna, resolving the contradiction between short signal path requirement and antenna integration.
2Object-affected harmful factors
If a shield is integrated in the contacting layer to decouple antenna from chip, then EMC shielding is improved, but device complexity increases
Solution Approach 1:
The contacting layer is designed to serve multiple functions simultaneously: it provides electrical connection between the chip and antenna through via connections, acts as an EMC shield by positioning conductive elements between the chip and antenna to prevent electromagnetic interference, and enables mechanical bonding between layers. By combining these functions into a single layer, the patent achieves effective shielding without proportionally increasing device complexity.
3Ease of manufacture
If redistribution layer is eliminated, then manufacturing complexity is reduced, but signal path routing flexibility is limited
Solution Approach 1:
The patent eliminates the need for redistribution layers by utilizing vertical via connections to route signals directly from the chip contact pads through the dielectric layer to the antenna layer. This vertical routing approach replaces the traditional planar redistribution layer routing, simplifying the manufacturing process while maintaining adequate signal path routing flexibility for the antenna connection.
Data Source
AI summary
A wafer level package with at least one integrated antenna element includes a chip layer with at least one chip, a dielectric layer as well as an antenna layer arranged between the chip layer and the dielectric layer.