Wafer-Level Light Emitting Device with Copper Pillars
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Solution Overview
Problem
Existing light emitting device technologies face challenges in downsizing and achieving high mass productivity due to requirements for high positional accuracy in bonding light emitting element chips to substrates, difficulties in forming small through holes in organic insulating films, and inefficiencies in the underfilling process with encapsulant materials, which hinder the replacement of traditional lighting sources with semiconductor-based solutions.
Innovation Solution
The implementation of a Wafer-Level Package (WLP) structure with copper pillars and reinforcing resin to maintain mechanical strength, reduce stress, and simplify the manufacturing process, allowing for downsized light emitting devices with reduced need for sealing resin and enabling assembly and inspection at the wafer level, thereby enhancing productivity and cost reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a light emitting element chip is flip-chip connected to an interconnect layer provided on a transparent substrate with high positional accuracy requirements, then bonding precision is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts and removes the complex interconnect layer from the device structure. Instead of using an interconnect layer on a transparent substrate, the invention directly bonds the light emitting element chip to a simplified substrate structure, eliminating the intermediate interconnect layer and its associated positioning complexity.
Solution Approach 2:
The patent inverts the conventional bonding approach by using a substrate with protrusions that directly engage with recesses in the chip, rather than using an interconnect layer with precise positioning features. This inversion simplifies the structure while maintaining bonding accuracy.
2Reliability
If small through holes are formed in organic insulating films during manufacturing, then electrical isolation is improved, but manufacturing difficulty and time increase
Solution Approach 1:
The patent eliminates the need to form small through holes in organic insulating films by using a different structural approach. The electrical isolation is achieved through the substrate design and bonding interface rather than through-hole formation, removing this difficult manufacturing step.
3Reliability
If underfilling process is used to fill volume between chip and substrate, then bonding reliability is improved, but manufacturing time and process complexity increase
Solution Approach 1:
The patent removes the underfilling process entirely from the manufacturing sequence. The bonding reliability is achieved through the mechanical interlocking design of the substrate protrusions and chip recesses, which provides inherent structural stability without requiring additional underfill material and processing steps.
4Productivity
If wafer-level packaging is implemented, then productivity is improved, but mechanical strength and stress management become critical challenges
Solution Approach 1:
The patent applies local quality by designing specific protrusion and recess features at the bonding interface to provide localized mechanical strength and stress distribution. The substrate includes protrusions with specific geometries that concentrate structural support where needed, enabling wafer-level processing while maintaining mechanical integrity.
Solution Approach 2:
The patent employs composite material structures in the substrate and bonding interface design, combining different materials with complementary properties to achieve both the mechanical strength required for wafer-level handling and the electrical isolation needed for device functionality.
Data Source
Figure 1A~1C
Figure 2A~2B
Figure 3A~3D
AI summary
A method for manufacturing a light emitting device includes: forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate; forming a dielectric film on a second surface side opposite to the first surface of the multilayer body, the dielectric film having a first and second openings on a p-side electrode and an n-side electrode provided on the second surface; forming a seed metal on the dielectric film and an exposed surface of the first and second openings; forming a p-side metal interconnect layer and an n-side metal interconnect layer on the seed metal; separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal, which is provided between the p-side metal interconnect layer and the n-side metal interconnect layer; and forming a resin in a space from which the seed metal is removed.