Wafer-Level Chip Packages With Preformed Metal Posts
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Solution Overview
Problem
Wafer-Level Packaging (WLP) for IC chips faces challenges in manufacturability and structural reliability due to increasing electrical connections and device density, leading to complexities in chip packaging and assembly processes.
Innovation Solution
The implementation of fine-pitched chip packages with preformed metal posts on the semiconductor substrate, encapsulated in a polymer material, and exposed for improved electrical performance, allowing for enhanced connectivity and reliability through metal bumps or wirebonding pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Wafer-Level Packaging (WLP) is used to reduce size and cost, then manufacturing efficiency and electrical performance improve, but structural reliability and manufacturability deteriorate due to increasing device density and connection complexity
Solution Approach 1:
The patent applies preliminary action by pre-forming metal posts on the semiconductor chip before packaging. These metal posts are prepared in advance and then connected to external contacts through the encapsulant, enabling reliable electrical connections without requiring complex post-packaging assembly processes. This preliminary preparation of connection structures resolves the contradiction by ensuring structural reliability is built into the package design from the outset, rather than attempting to achieve it through complex assembly procedures.
Solution Approach 2:
The patent uses the encapsulant as an intermediary material that fills the space between the chip and the external contacts. This encapsulant medium enables electrical connection through the chip while providing mechanical support and protection. The intermediary encapsulant resolves the contradiction by simultaneously enabling the simplified WLP structure (improving productivity) while providing the necessary mechanical and electrical pathways for reliable connections (improving structural reliability).
2Adaptability or versatility
If device density and connection number increase to achieve higher integration, then functional capability improves, but manufacturing complexity and assembly difficulty increase
Solution Approach 1:
The patent transitions from planar two-dimensional connections to three-dimensional vertical connections by extending metal posts through the encapsulant. This dimensional change allows multiple high-density connections to be made in the vertical direction rather than requiring complex lateral routing. The third dimension resolves the contradiction by enabling high device integration (more connections) while simplifying the packaging and assembly process through straightforward vertical bonding operations.
Solution Approach 2:
The patent implements self-service by having the metal posts on the chip directly serve as the connection interface for external contacts. The chip's own metal posts perform the dual function of electrical connection and mechanical anchoring, eliminating the need for separate complex interconnection structures. This self-service approach resolves the contradiction by enabling high integration through direct chip-to-package connections while reducing packaging and assembly complexity.
Data Source
AI summary
Chip assemblies are disclosed that include a semiconductor substrate, multiple devices in and on the semiconductor substrate, a first metallization structure over the semiconductor substrate, and a passivation layer over the first metallization structure. First and second openings in the passivation layer expose first and second contact pads of the first metallization structure. A first metal post is positioned over the passivation layer and over the first contact pad. A second metal post is positioned over the passivation layer and over the second contact pad. A polymer layer is positioned over the passivation layer and encloses the first and second metal posts. A second metallization structure is positioned on the polymer layer, on the top surface of the first metal post and on the top surface of second metal post. The second metallization structure includes an electroplated metal. Related fabrication methods are also described.