Wafer Level Package Substrate with Die-Matching Size
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Solution Overview
Problem
Conventional wafer level packages use photo-dielectric materials for layer-to-layer passivation and connection, which are thinner and physically weaker than substrate cores, and result in larger package sizes compared to semiconductor dies, posing challenges in critical size applications and sensor interconnection methods.
Innovation Solution
A semiconductor package design featuring a substrate with a redistribution layer, mold compound encapsulation, and interconnects to match the size of the semiconductor die, utilizing conventional die bonding and reflow processes, and incorporating a piezoelectric layer for sensor applications, allowing for a more robust and reliable assembly with reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photo-dielectric material is used for layer to layer passivation and connection, then the package can be manufactured with conventional processes, but the material is thinner and physically weaker than substrate cores
Solution Approach 1:
The patent uses a substrate core made of strong material (e.g., ceramic or metal) combined with photo-dielectric materials for passivation layers. This composite structure provides both the mechanical strength of the substrate core and the manufacturability benefits of photo-dielectric materials for conventional processing and layer-to-layer connections.
2Reliability
If conventional substrate based and leadframe based packages are used, then the package can provide robust interconnection, but the package size is bigger than semiconductor dies
Solution Approach 1:
The patent merges the semiconductor die directly with the substrate in a co-fired or co-bonded structure, eliminating the need for separate leadframes or large substrate assemblies. This integration achieves both small package size (matching the die footprint) and reliable interconnection through direct bonding and embedded interconnects.
Solution Approach 2:
The patent transitions from planar two-dimensional packaging to three-dimensional vertical stacking with multiple layers of interconnects and passivation. This allows robust interconnection to be achieved in the vertical dimension while maintaining a small footprint in the horizontal plane, matching the semiconductor die size.
3Area of moving object
If wafer level package is used to reduce package size, then the package size matches semiconductor die, but photo-dielectric material is physically weaker
Solution Approach 1:
The patent employs a composite structure where a strong substrate core (ceramic or metal) provides mechanical strength, while photo-dielectric materials are used for passivation and interconnection layers. This combination enables wafer-level packaging with die-matching size while compensating for the weakness of photo-dielectric materials through the robust substrate core.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a thinner, smaller package size matching the semiconductor die, enhanced assembly reliability, and improved interconnection methods for sensor applications, while minimizing die and substrate loss and manufacturing costs through known-good substrate and die assemblies.
Implementation Method 1
a piezoelectric layer for sensor applications
Data Source
AI summary
A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.