Wafer Level Package Via Insulation for Thermal Management
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Solution Overview
Problem
Current wafer level packaging for electronic devices, such as LEDs, is costly due to the requirement of a carrier chip, which doubles or triples the heat resistivity and increases production costs, necessitating a packaging solution that eliminates the need for a carrier chip while providing an insulated connection path.
Innovation Solution
A wafer level package is developed where a vertical interconnect access (VIA) is created through a substrate to connect the electronic device, using a pass through hole with an insulated passivation layer and a metal layer for electrical contact, allowing the electronic device to be directly attached to the substrate without a carrier chip, utilizing a substrate with a first and second face and an electrically insulating passivation layer for insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a carrier chip is used for wafer level packaging, then electrical connection to the electronic device is achieved, but the heat resistivity increases and packaging cost increases
Solution Approach 1:
The patent removes the carrier chip from the packaging structure entirely, extracting the problematic intermediate layer that caused high heat resistivity. The electronic device is directly mounted on the substrate with electrical connections made through vias in the substrate, eliminating the carrier chip's thermal barrier effect.
Solution Approach 2:
The patent creates an asymmetric thermal path by using different materials and structures for thermal management on each side of the substrate. The substrate itself serves as the thermal management layer with optimized thermal conductivity, while the top side accommodates the electronic device without requiring a symmetric carrier chip structure.
2Reliability
If a carrier chip is used for wafer level packaging, then electrical connection to the electronic device is achieved, but packaging cost increases
Solution Approach 1:
The patent eliminates the carrier chip component entirely, reducing the bill of materials and assembly steps. The substrate directly provides both mechanical support and electrical connection functions, removing the need for a separate carrier chip and its associated bonding and mounting processes.
Solution Approach 2:
The patent merges the functions of the carrier chip and substrate into a single integrated substrate structure. The substrate simultaneously provides mechanical support, electrical connection pathways through vias, and thermal management, eliminating the need for a separate carrier chip and reducing overall packaging complexity and cost.
3Reliability
If an insulated passivation layer is formed to cover the pass through hole, then electrical insulation between the metal layer and substrate is provided, but the manufacturing process complexity increases
Solution Approach 1:
The patent uses a thin film passivation layer deposited conformally on the substrate surface and inside the via holes. This thin film approach provides effective electrical insulation while adding minimal complexity to the manufacturing process, as it can be applied using standard thin film deposition techniques already present in semiconductor fabrication.
Solution Approach 2:
The patent controls the thickness and material properties of the passivation layer to optimize both insulation performance and manufacturing simplicity. By carefully selecting the passivation material and controlling its deposition parameters, the process achieves reliable electrical insulation without requiring overly complex multi-layer or thick-film structures.
Data Source
AI summary
Aspects of the invention are directed to an electronic device package including an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer.