Wafer Level Package Via Hole Interconnect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging methods require complex and costly processes, leading to increased fabrication costs, defective products, and mechanical instability due to protruding interconnection structures, which also result in increased package thickness and space between components.
Innovation Solution
A wafer level package is fabricated by forming semiconductor chips with a redistribution structure and a connecting device that penetrates through a via hole, allowing for reduced thickness and improved reliability, with a trench formed on the wafer and a connecting device formed using electroplating and solder jet processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional interconnection structure with protruding parts is used to penetrate the semiconductor chip, then electrical connection between package units is achieved, but mechanical stress concentrates on the protruding part causing breakage and increased package thickness
Solution Approach 1:
The patent extracts the protruding interconnection structure from the semiconductor chip by forming a recess (via hole) that accommodates the interconnection structure. The interconnection structure is taken out from a protruding configuration and embedded into the chip substrate, eliminating the weak protruding part that concentrates mechanical stress while maintaining electrical connection functionality.
2Reliability
If solder bumps are formed at the bottom surface of package units to secure electrical connection stability, then electrical connection is improved, but the space between package units and overall package thickness increase
Solution Approach 1:
The patent applies nesting by embedding the interconnection structure within the semiconductor chip substrate through a via hole recess. The interconnection structure is nested inside the chip rather than protruding outward, allowing electrical connections to be made at the same level as the chip surface, thereby reducing package thickness while maintaining connection stability.
3Reliability
If a via hole penetrating the entire semiconductor chip is formed to create an interconnection structure, then electrical connection through the chip is achieved, but the fabricating process becomes complicated and costly
Solution Approach 1:
The patent uses partial action by forming a via hole that penetrates only part of the semiconductor chip thickness rather than completely through the entire chip. The via hole extends from the bottom surface to a depth that exposes the bottom surface of the connection pad, which is sufficient to establish electrical connection without requiring excessive material removal or complex multi-step fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs, lowers overall package thickness, and enhances reliability by minimizing mechanical stress on interconnection structures, while maintaining high performance and small form-factor requirements.
Implementation Method 1
a connecting device formed using electroplating and solder jet processes
Implementation Method 2
a connecting device formed using electroplating and solder jet processes
Data Source
AI summary
Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.