Wafer-Level System-In-Package Staggered Chip Embedding
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Solution Overview
Problem
Current wafer-level system-in-package (WLSiP) technologies face challenges in efficiently integrating multiple chips and optimizing electrical performance while reducing package area and manufacturing costs.
Innovation Solution
A WLSiP package structure and method that involves a substrate with first chips grown on it, embedding second chips within an encapsulation layer, and forming electrical connections between the two types of chips, which are staggered to minimize space and enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are integrated using conventional SiP methods, then functional complexity is improved, but package area and manufacturing cost increase
Solution Approach 1:
The patent embeds second chips within the encapsulation layer at different depths, creating a nested three-dimensional structure where chips are arranged at multiple levels rather than flat planes. This vertical stacking approach significantly reduces the horizontal package area while maintaining the ability to integrate multiple functional components.
Solution Approach 2:
The invention transitions from conventional two-dimensional planar arrangement of chips to a three-dimensional configuration by embedding chips at different depths within the encapsulation layer. This dimensional change allows for higher integration density without increasing the footprint of the package.
2Productivity
If wafer-level packaging is implemented, then manufacturing efficiency is improved, but integration complexity of multiple chip types increases
Solution Approach 1:
The patent divides the integration process into distinct segments: first chips are grown on the substrate in a wafer-level batch process, then second chips are separately prepared and subsequently embedded into the encapsulation layer. This segmentation allows each chip type to be optimized independently while maintaining batch manufacturing advantages for the first chips.
Solution Approach 2:
The first chips are pre-grown on the substrate using wafer-level semiconductor manufacturing processes before the encapsulation layer is formed. This preliminary action enables batch production of the substrate assembly, maintaining manufacturing efficiency while allowing subsequent flexible integration of different second chip types.
3Area of stationary object
If chips are arranged in staggered configuration, then space utilization is improved, but electrical connection complexity increases
Solution Approach 1:
The encapsulation layer serves as an intermediary structure that facilitates electrical connections between chips at different levels. It provides a medium for embedding conductive elements, vias, and interconnect structures that bridge the staggered chip positions, managing the complexity of three-dimensional electrical interconnections.
Solution Approach 2:
The patent extracts the electrical connection function from the mechanical arrangement by using separate conductive pathways and interconnect structures within the encapsulation layer. This allows the staggered spatial configuration to be optimized for area reduction while electrical connections are independently routed through the encapsulation medium, decoupling spatial and electrical design constraints.
Data Source
AI summary
The present disclosure provides a wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure. The WLSiP package structure includes a device substrate including a substrate and a plurality of first chips on the substrate, an encapsulation layer, covering the device substrate, a plurality of second chips embedded in the encapsulation; and an electrical connection structure, electrically connecting at least one of the plurality of second chips with at least one of the plurality of first chips. The plurality of first chips and the plurality of second chips are staggered from each other.