Cache Way Prediction with WLUT for Lower Access Energy
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Solution Overview
Problem
Conventional set-associative caches in processor-based devices waste energy by probing all ways in parallel for data access, leading to significant energy dissipation and increased static power consumption as memory circuits become denser.
Innovation Solution
Implement a way lookup table (WLUT) circuit that predicts the correct way to access in a cache memory device, reducing energy consumption by accessing only the predicted tag and data ways, and utilize a fast EA generation circuit and drowse circuits to optimize energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional set-associative caches probe all ways in parallel to minimize access time, then memory access speed is improved, but energy consumption increases significantly
Solution Approach 1:
The WLUT circuit performs preliminary action by predicting the correct way before the actual memory access occurs. It uses historical data and access patterns to pre-determine which way is most likely to contain the requested data, allowing the cache controller to access only the predicted way rather than probing all ways in parallel, thus reducing energy consumption while maintaining acceptable access speed
Solution Approach 2:
The WLUT circuit acts as an intermediary between the memory access request and the cache controller. It receives the memory access request, determines the predicted way using its lookup table, and provides this prediction to the cache controller, which then accesses only the predicted way. This intermediary mechanism eliminates the need for parallel probing of all ways while ensuring correct data retrieval
2Loss of time
If set-associative caches are configured to probe all ways in parallel, then data retrieval time is minimized, but static power consumption increases
Solution Approach 1:
The WLUT circuit performs preliminary determination of the correct way before the memory access operation. By using historical access patterns and storing this information in its lookup table, the WLUT can predict the correct way in advance, allowing the cache controller to activate only the necessary way rather than keeping all ways in a ready state for parallel access, thus reducing static power consumption
Solution Approach 2:
The invention changes the operational parameter from parallel probing of all ways to sequential access of a predicted way. The WLUT circuit modifies the access pattern by determining the most likely way based on historical data, transforming the cache access from a parallel search to a targeted access, which reduces the time window during which multiple ways need to be active and consequently reduces static power consumption
Data Source
AI summary
Optimizing cache energy consumption in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a way lookup table (WLUT) circuit that is configured to receive an effective address (EA) for a memory access request. The WLUT circuit determines that a tag portion of the EA corresponds to a tag of a WLUT entry among a plurality of WLUT entries. In response, the WLUT circuit transmits a predicted way indicator of the WLUT entry to a cache controller. The cache controller accesses, in a set among a plurality of sets of a cache memory device corresponding to a set portion of the EA, only a predicted tag way among a plurality of tag ways of the cache memory device indicated by the predicted way indicator and only a predicted data way among a plurality of data ways of the cache memory device indicated by the predicted way indicator.