Dual-Mode WOM Codec With ECC Syndrome Reuse

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Solution Overview

Problem

Existing memory devices, such as electrically erasable read-only memories, are unsuited for certain applications due to increased cost and decreased performance characteristics, particularly in systems requiring non-volatile memory with efficient write and read capabilities.

Innovation Solution

A dual-mode error correction code (ECC) and write-once memory (WOM) coding and decoding system that includes a controller for selecting between ECC and WOM modes, utilizing a codec that operates in both modes to identify bit errors and encode/decode data, allowing for efficient writing and reading in non-volatile memory without erasure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If electrically erasable read-only memory is used to provide non-volatile memory with write and read capabilities, then the ability to write and read data is improved, but cost increases and performance characteristics decrease

Engineering Contradiction:

Improvewrite and read capabilityVSAvoidperformance characteristics

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The memory system is designed to operate in two distinct modes: Write-Once Memory (WOM) mode for high-endurance write operations and Error Correction Code (ECC) mode for reliable data storage. The same memory device can be configured for different operations depending on the application requirements, providing multi-functionality that addresses both write capability and performance reliability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system changes operational parameters by switching between WOM mode and ECC mode. In WOM mode, the focus is on write endurance with limited error correction, while in ECC mode, full error correction is enabled for maximum reliability. This parameter switching allows the system to optimize performance characteristics for different operational contexts

Inventive Principle:

Principle #35Parameter changes

2Reliability

If error correction code is implemented to correct bit errors, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvebit error correctionVSAvoidcodec complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The codec dynamically switches between WOM mode and ECC mode based on operational requirements. This dynamic operation allows the system to implement full error correction capabilities when needed while simplifying operations during normal write cycles, thereby managing complexity adaptively rather than statically

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

In WOM mode, the system performs partial error correction suitable for write operations, while reserving full ECC capabilities for read operations or critical data storage. This partial action approach provides adequate error correction for each operational context without always invoking the full complexity of ECC processing

Inventive Principle:

Principle #16Partial or excessive action

3Productivity

If write-once memory is used to enable multiple writes without erasure, then productivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvewrite enduranceVSAvoidmemory cell precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The system incorporates error correction codes and verification mechanisms before data is committed to the memory cell. This beforehand cushioning ensures that even if manufacturing variations cause slight precision issues, the error correction capabilities will detect and correct potential errors, protecting against manufacturing imprecision

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9690517B2Dual-mode error-correction code/write-once memory codec

Publication Date: 2017.06.27 TEXAS INSTRUMENTS INC

AI summary

A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.