Word Buffer Bit Correction for High-Throughput Product Code Decoding
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Solution Overview
Problem
Existing error correction codes (ECC) in memory devices are costly and complex, requiring significant space and power, which is a challenge for devices with limited area and power budgets, and removing ECC can increase the probability of data loss and failure.
Innovation Solution
The use of a product code decoder (PCD) and bit correction circuit to efficiently perform error correction in memory devices, utilizing a product code and BCH component codes to achieve error correction with reduced hardware complexity and power consumption, while maintaining high error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC mechanisms (LDPC, BCH, Reed-Solomon) are used for error correction, then error correction capability is improved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent segments the error correction process into two distinct phases: a fast path for single-bit errors using simple inversion logic, and a slow path for multi-bit errors using comprehensive syndrome decoding. This segmentation allows the system to handle the majority of common error cases with minimal hardware complexity while maintaining the capability to correct more complex errors when needed.
Solution Approach 2:
The patent implements partial action by applying full syndrome decoding only when necessary (when fast path correction fails or multiple errors are detected), rather than always performing complete decoding. This reduces average-case hardware complexity and power consumption while maintaining reliability for all error scenarios.
2Reliability
If traditional ECC mechanisms are used for error correction, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The error correction logic is segmented into low-power fast path operations (single bit inversion) and high-power slow path operations (syndrome decoding). By routing single-bit errors through the fast path, the system dramatically reduces power consumption for the common case while maintaining full error correction capability through the slow path when needed.
Solution Approach 2:
The system performs partial error correction actions for single-bit errors using only inversion logic, avoiding the power-intensive syndrome decoding process. This partial action approach suffices for single-bit errors and significantly reduces power consumption while the complete decoding capability remains available for multi-bit errors.
3Reliability
If comprehensive syndrome decoding is performed for all errors, then error correction accuracy is improved, but processing time increases
Solution Approach 1:
The patent segments error correction into a fast path for single-bit errors and a slow path for multi-bit errors. This segmentation enables the system to achieve high-speed correction for the majority of error cases while maintaining accurate correction for more complex error patterns through the comprehensive slow path decoding.
Solution Approach 2:
For single-bit errors, the system performs partial correction using only fast path inversion, avoiding the time-consuming syndrome decoding process. This partial action achieves sufficient correction accuracy for single-bit errors while dramatically reducing processing time, whereas the complete decoding process remains available when higher accuracy is needed for multi-bit errors.
Data Source
AI summary
A product code decoder to implement a method of bit correction in a codeword buffer to support error correcting code (ECC). The method loads a location entry from a correction queue, where the location entry includes a data word address and bit location information. The method performs a fast path data word address comparison to determine whether data from the data word address is being processed by a previous entry from the correction queue. The method further combines a correction of the data at the data word address specified by the location entry with a correction of a copy of the data being processed based on a previous location entry, in response to a fast path data word address comparison match, and stores the combined data in the codeword buffer.