Word Concatenation Deinterleaving for Turbo Decoder Throughput
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Solution Overview
Problem
Turbo decoders in telecommunications systems face inefficiencies in memory usage and throughput due to the need for large look-up tables and sequential processing of de-interleaved data, particularly in systems like 3GPP LTE, which limits data throughput and requires extensive memory resources.
Innovation Solution
An apparatus and method utilizing a read circuit and logic network to generate de-interleaved data words by concatenating sections of words, avoiding the use of look-up tables and optimizing memory usage by spreading memory across multiple instances, allowing for faster processing and efficient resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If look-up tables are used to ensure correct bit selection order in de-interleaving, then de-interleaving accuracy is improved, but memory resource consumption increases significantly
Solution Approach 1:
The de-interleaving process is segmented into multiple passes, with each pass handling a specific portion of the de-interleaved word. Instead of storing all bit position mappings in a single large look-up table, the system divides the work into sequential steps that process different segments of the data, reducing peak memory requirements while maintaining accuracy.
Solution Approach 2:
The system performs preliminary actions by pre-calculating and storing only the essential mapping information needed for each pass in a compact format. Rather than storing complete look-up tables for all possible bit positions, the system pre-processes the mapping relationships into a condensed representation that fits within limited memory resources.
2Measurement precision
If sequential bitwise de-interleaving is used to ensure correct bit selection, then de-interleaving accuracy is improved, but processing speed decreases
Solution Approach 1:
The de-interleaving operation is divided into multiple parallel passes, where each pass processes a specific subset of bits simultaneously. This segmentation allows the system to maintain the correctness of bit selection while achieving parallel processing speedups, as each pass can operate independently on its assigned portion of the data.
Solution Approach 2:
Multiple parallel processing passes are merged to produce the complete de-interleaved output. The system combines the results from several simultaneous operations, each handling a different portion of the de-interleaved word, thereby achieving both high processing speed and accurate bit selection through coordinated parallel execution.
3Ease of manufacture
If a single large memory block is used to store the entire data block, then memory allocation is simplified, but memory resource efficiency decreases
Solution Approach 1:
The large data block is segmented into smaller sub-blocks that can be stored in distributed memory locations. This segmentation allows the system to use multiple smaller memory resources instead of requiring one large contiguous memory block, improving memory resource efficiency while maintaining the ability to access and process the complete data set through coordinated access patterns.
Data Source
AI summary
An apparatus for producing a word of a de-interleaved sequence of bits from a sequence of bits stored in a memory is described. In one embodiment, the apparatus includes a read circuit for selecting bits of the stored sequence and forming the selected bits into a word, and a logic network arranged to produce the word of the de-interleaved sequence by concatenating sections of a plurality of words produced by the read circuit. The technique can also be used to achieve interleaving, rather than de-interleaving, of a data sequence.