Word-Level Netlist Loop Handling in EDA Tools
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Solution Overview
Problem
Existing clock-domain tools face inefficiencies in traversing combinational loops in word-level netlists, leading to resource-intensive computations and prolonged verification times, especially when implementing hierarchical verification schemes.
Innovation Solution
The tools identify combinational loops in a word-level netlist by analyzing loop characteristics, translating selected portions into bit-level representations, and modifying the netlist by replacing loops with loop buffers or annotating their presence, thereby reducing computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock-domain tool traverses combinational loops in the word-level netlist to perform static checks, then verification completeness is improved, but computational resource consumption and traversal time increase significantly
Solution Approach 1:
The patent segments the combinational loop traversal problem by identifying and extracting loop structures from the word-level netlist, separating them into identifiable components. This allows the verification tool to handle loop portions differently from acyclic portions, applying optimized traversal strategies specifically to loop structures while maintaining comprehensive verification coverage.
Solution Approach 2:
The patent performs preliminary identification and annotation of combinational loop structures in the netlist before the main verification traversal. By pre-processing the netlist to mark loop portions and establish loop boundaries, the tool avoids redundant computation during the actual verification process, significantly reducing traversal time while maintaining completeness.
2Measurement precision
If the clock-domain tool performs comprehensive static checks on all combinational loops, then verification accuracy is improved, but resource consumption increases
Solution Approach 1:
The patent applies different verification strategies to different portions of the netlist based on their structural characteristics. Loop portions receive specialized handling with optimized traversal methods, while acyclic portions use standard verification approaches. This localized differentiation maintains verification accuracy for critical loop structures while reducing overall resource consumption.
Solution Approach 2:
The patent changes the traversal parameters and methods when encountering combinational loop structures versus acyclic structures. By detecting loop characteristics and switching to optimized traversal algorithms specifically designed for cyclic dependencies, the tool maintains verification accuracy while significantly reducing the computational resources required for loop portions.
3Reliability
If the clock-domain tool implements hierarchical verification with multiple netlist traversals, then verification thoroughness is improved, but the presence of combinational loops exacerbates resource consumption and time requirements
Solution Approach 1:
The patent segments the hierarchical verification process by identifying loop structures at different hierarchy levels and applying specialized handling to loop portions. This segmentation allows each hierarchical level to focus on its specific scope while the loop identification mechanism ensures consistent handling of cyclic dependencies across all levels, reducing the complexity burden of multiple traversals.
Solution Approach 2:
The patent performs preliminary loop identification and annotation at the beginning of the hierarchical verification process, before the multiple hierarchical traversals begin. This pre-processing establishes a loop map that can be reused across all hierarchical levels, eliminating the need to rediscover and re-analyze loop structures during each traversal, thereby reducing overall process complexity.
Data Source
AI summary
This application discloses an electronic design automation tool configured to identify combinational loops in a word-level netlist, and then modify the word-level netlist based on the presence of the combinational loops. The electronic design automation tool can analyze the word-level netlist to identify a portion of the word-level netlist having at least one characteristic associated with a combinational loop, translate the identified portion of the word-level netlist into a bit-level circuit representation, and utilize the bit-level circuit representation to determine whether the identified portion of the word-level netlist implements the combinational loop. The electronic design automation tool can modify the word-level netlist by replacing the identified combination loop in the word-level netlist with a description of a different circuit, such as a loop buffer, or annotate the presence of the identified combinational loop in the word-level netlist.