Word-Level Netlist Preprocessing for Hardware Verification
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Solution Overview
Problem
Current model checking technologies are inefficient for verifying complex hardware designs with wide datapaths and large memories, as they require extensive user annotations and computations that are as difficult as the original problem, and do not effectively handle sequential systems or unbounded properties.
Innovation Solution
A method for preprocessing circuit representations to convert bit-level signals into word-level signals, allowing for the creation of a reduced netlist that can be analyzed using standard verification tools, which includes segmenting and converting nodes in a directed acyclic graph data structure to identify reduced safe sizes and preserve property provability, without requiring user annotations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard model checking is used for wide datapaths and large memories, then verification completeness is maintained, but computing resource consumption increases significantly
Solution Approach 1:
The patent segments the datapath into multiple word-level components, allowing the verification system to process each segment independently at a higher abstraction level. This segmentation enables the use of word-level variables and operations in the model checker, reducing the state space that needs to be explored while maintaining verification completeness for the segmented portions.
Solution Approach 2:
The patent changes the parameter of abstraction level from bit-level to word-level for specific portions of the design. By allowing the model checker to operate at word-level for segmented datapaths, the state space is dramatically reduced, lowering computing resource consumption while maintaining verification effectiveness for those portions.
2Productivity
If user annotations are used to speed up model checking, then verification speed improves, but design time increases due to annotation effort
Solution Approach 1:
The patent implements automatic segmentation of the datapath into word-level components without requiring user annotations. The verification system autonomously identifies suitable segmentation points and transforms the design representation, eliminating the manual annotation effort while maintaining the speed benefits of word-level verification.
Solution Approach 2:
The patent performs preliminary automatic segmentation and transformation of the design into a format suitable for word-level verification before the actual model checking begins. This preliminary processing eliminates the need for user annotations during the verification process while preparing the design for faster word-level analysis.
3Measurement precision
If bit-level analysis is used for sequential systems, then detailed verification is achieved, but analysis time increases for unbounded properties
Solution Approach 1:
The patent segments the sequential system into word-level components, allowing the model checker to operate at a higher abstraction level for portions of the design. This segmentation maintains verification detail for the segmented portions while dramatically reducing the analysis time required for unbounded properties by avoiding bit-level exploration of the entire state space.
Data Source
AI summary
A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are converted into bit-level nodes. The segmented nodes are analyzed to define reduced safe sizes by applying a computer implemented function. An updated data structure representing the circuit design is then generated using the reduced safe sizes of the segmented nodes.