Word Level Power Gating in Memory Arrays
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Solution Overview
Problem
Existing low-power memory designs, such as array-level power gating, are inefficient when only a small portion of a memory array needs to remain active, as they fail to effectively manage power consumption at a fine granularity.
Innovation Solution
The implementation of fine-grained power gating in memory arrays by adding an extra control bit to each subarray, allowing for independent power control of each word, row, or bitline, using gating transistors and power control memory cells to enable or disable power to specific memory cells, mimicking the access and writing of regular memory bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If array-level power gating is used, then power consumption is reduced at the array level, but power management efficiency deteriorates when only a small portion of the memory array needs to remain active
Solution Approach 1:
The memory array is divided into multiple independently power-gatable subarrays or blocks. Each subarray has its own power gating control, allowing selective powering down of unused portions while keeping active portions operational. This segmentation enables fine-grained power management where only the necessary memory portions remain active, resolving the contradiction between achieving power reduction and maintaining power management efficiency.
2Measurement precision
If fine-grained power gating is implemented by adding control bits and gating transistors, then power control precision is improved, but device complexity increases
Solution Approach 1:
The memory array is segmented into multiple power-gatable blocks, each with its own control bit and gating transistor. This segmentation enables precise power control for each block independently, achieving fine-grained power management while keeping the complexity increase manageable through modular design.
Solution Approach 2:
The power gating control mechanism is designed to be universal across all memory blocks, using the same control bit and gating transistor structure for each block. This multi-functionality approach allows the same design to be replicated across multiple blocks, achieving precise power control while reducing overall design complexity through standardization.
Data Source
AI summary
In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).