Word Line Address Scan Testing for Flash Memory
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Solution Overview
Problem
Conventional word line address scan systems face challenges in testing whether a single word line is correctly selected, if the word line voltage reaches a target level within a specified time, and ensuring no other word lines are selected, due to voltage mismatches and lack of efficient disaster checks, especially in non-volatile memories like Flash.
Innovation Solution
A system and method that includes a word line address scan with a Wired OR circuit to detect the selection of one or multiple decoder outputs, a timing verification circuit to assess word line rise time, and a pre-address decoder for address transition detection, allowing for testing of one or multiple parameters, including low and high voltage scans to detect failures before the word line signal enters the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional address decoder and memory array are used, then the system can perform basic memory operations, but voltage mismatch between address decoder and memory array makes testing difficult
Solution Approach 1:
A voltage level shifter circuit is introduced as an intermediary component between the address decoder operating at first voltage levels and the memory array operating at second voltage levels. This level shifter translates address signals from the first voltage domain to the second voltage domain, enabling proper signal transmission and making testing reliable without requiring the entire system to operate at multiple complex voltage levels simultaneously.
2Reliability
If comprehensive testing of all word line parameters is performed, then complete verification is achieved, but testing time and system complexity increase significantly
Solution Approach 1:
The word line testing function is divided into separate dedicated circuits: a wired OR circuit for detecting multiple word line selections, a timing verification circuit for measuring rise time, and a pre-address decoder for detecting address transitions. This segmentation allows each aspect to be tested independently and efficiently, reducing overall testing time while maintaining comprehensive verification capability.
Solution Approach 2:
The pre-address decoder performs preliminary detection of address transitions before the main word line selection process. By detecting address changes in advance, the system can prepare for upcoming word line activations and perform timing verification proactively, reducing the critical path delay and overall testing time.
3Productivity
If fast disaster checks are implemented for safety applications, then quick detection is achieved, but additional circuitry increases system complexity
Solution Approach 1:
The wired OR circuit combines multiple word line signals into a single output that indicates whether any word line is selected. This merging approach enables fast disaster checks by providing immediate feedback on word line selection status without requiring complex individual monitoring circuits for each word line, thus achieving high-speed safety checks with minimal additional circuitry.
4Ease of operation
If voltage level shifter is added to bridge voltage mismatch, then signal transmission between address decoder and memory array is enabled, but device complexity and cost increase
Solution Approach 1:
The voltage level shifter circuit is designed to handle multiple address signals simultaneously and can be configured for different voltage level transitions. This multi-functional design allows a single circuit implementation to serve various testing and operational modes, reducing the need for separate circuits for each function and thereby limiting the increase in overall device complexity.
Data Source
AI summary
A system and method for performing three scans for testing an address decoder and word line drive circuits is disclosed. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected.