Word Line Buffer Circuit With Thin-Oxide Pull-Down for Lower GIDL
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Solution Overview
Problem
As semiconductor memory devices trend towards high integration and high capacity, the substantial electric field intensity from boosted voltages in MOS transistors leads to increased gate-induced drain leakage (GIDL), deteriorating device characteristics and productivity due to high voltage differences between the gate and drain/source in MOS transistors.
Innovation Solution
A buffer circuit design that includes NMOS and PMOS transistors with thinner gate oxide layers for the pull-down element, reducing voltage differences between the gate and drain/source in standby mode and applying a lower voltage to the gate in active mode, thereby reducing leakage currents and improving operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker gate oxide layer is used in the NMOS transistor to withstand the boosted voltage VPP at the gate, then the transistor can operate in active mode without breakdown, but the operating speed decreases due to increased gate capacitance and reduced carrier mobility
Solution Approach 1:
The patent applies different gate oxide layer thicknesses to different transistor types within the same buffer circuit. Specifically, the PMOS transistor uses a first gate oxide layer thickness optimized for its operation, while the NMOS transistor uses a second gate oxide layer thickness (different from the first) optimized for its operation with boosted voltage. This local differentiation allows each transistor to have optimal performance characteristics for its specific voltage conditions, resolving the contradiction between reliability and speed.
2Device complexity
If the buffer circuit uses conventional transistor design with uniform gate oxide thickness, then the circuit structure is simple, but the leakage current increases due to GIDL effect from large voltage differences between gate and drain
Solution Approach 1:
The patent implements different gate oxide layer thicknesses for PMOS and NMOS transistors to locally optimize their electrical characteristics. The NMOS transistor, which experiences larger voltage differences and higher GIDL effects, uses a gate oxide thickness specifically optimized to reduce leakage current. This local optimization reduces the harmful GIDL effect without requiring complex circuit modifications.
Solution Approach 2:
The patent changes the physical parameter of gate oxide layer thickness to optimize transistor performance under different voltage conditions. By adjusting the gate oxide thickness parameter for each transistor type, the circuit achieves reduced leakage current and improved operating characteristics without increasing structural complexity.
3Productivity
If the buffer circuit is designed for high integration and high capacity, then the device density increases, but the electric field intensity increases leading to higher GIDL and deteriorated device characteristics
Solution Approach 1:
The patent applies different gate oxide thicknesses to different transistor locations and types within the high-density integrated circuit. This local optimization allows the circuit to maintain high integration density while reducing GIDL effects in specific transistors that are more susceptible to the effect, thereby improving overall device characteristics without sacrificing productivity.
Solution Approach 2:
By changing the gate oxide thickness parameter in the transistor design, the patent reduces the electric field intensity at the drain-gate junction, thereby reducing GIDL effects. This parameter optimization enables high-density integration while maintaining acceptable device characteristics and reducing harmful leakage currents.
Data Source
AI summary
A buffer circuit includes a pull-up element configured to pull-up drive a first node through which an output signal is outputted, in response to an input signal; a first voltage control element configured to reduce a voltage of the first node and set a voltage of a second node in a standby mode; and a pull-down element configured to pull-down drive the second node in response to the input signal.