Word Line Clamp Control for Low-Leakage Memory Sleep States
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face challenges in simplifying power shutoff control and reducing the area occupied by control circuits while minimizing leak currents and preventing data corruption during sleep states.
Innovation Solution
A semiconductor integrated circuit device with a driver circuit connected to a memory cell array via a word line, a clamp element between the word line and ground potential, and a control circuit that controls the clamp element through a first and second circuit, where the switch element in the power supply route is shut off during sleep to reduce leak currents and maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power shutoff circuits are formed separately between MOS circuits at odd-numbered stages and even-numbered stages, then leak currents can be reduced during sleep, but the design becomes difficult and the control circuit area increases
Solution Approach 1:
The patent merges the power shutoff control for odd-numbered and even-numbered MOS circuits into a single unified control circuit. The control circuit uses a single control signal to simultaneously control the shutoff of power supply to both odd and even stages, eliminating the need for separate control circuits while still achieving leak current reduction during sleep mode.
Solution Approach 2:
The control circuit is designed to perform multiple functions: it controls power shutoff for both odd and even numbered MOS circuits, manages sleep mode transitions, and prevents data corruption during state transitions. This multi-functional design reduces the overall circuit area while maintaining effective leak current suppression.
2Loss of energy
If separate power shutoff circuits are used for odd and even stages, then leak currents are reduced, but the control circuit area increases
Solution Approach 1:
The patent combines the control logic for power shutoff into a single integrated control circuit that manages both odd and even numbered MOS circuits. This merging approach reduces the total control circuit area compared to having separate control circuits for each stage, while still achieving effective leak current reduction through unified power shutoff control.
3Reliability
If power supply timing is differentiated between odd and even stages, then data corruption is prevented, but the control becomes complex
Solution Approach 1:
The control circuit is designed to preliminarily control the power shutoff timing for all MOS circuits before state transitions occur. By establishing a unified control signal that preemptively manages power supply to both odd and even stages, the circuit prevents data corruption during sleep mode transitions without requiring complex differentiated timing control.
Data Source
AI summary
A semiconductor integrated circuit device includes: a driver circuit connected to a memory cell array via a word line; a clamp element provided between the word line and a ground potential; and a control circuit having a first circuit that turns ON/OFF the clamp element and a second circuit connected at its output to an input of the first circuit. A first power supply node supplying first power is connected to the first circuit, and a second power supply node connected to the first power supply node via a switch element is connected to the driver circuit and the second circuit.