Protruding Word Line Structure for Shallower DRAM Contact Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The etching process for forming contact holes in DRAM structures increases the etching depth, leading to damage in the active region and bit line, affecting electrical isolation performance and increasing leakage current, which reduces yield and electrical performance.
Innovation Solution
A semiconductor structure is formed with a word line having a first and second portion, where the second portion protrudes perpendicularly from the first, allowing for reduced etching time and depth, thereby minimizing damage to the active region and bit line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If contact holes are simultaneously etched for active region, peripheral gate region, bit line, and word line, then the manufacturing process is simplified, but the etching depth increases causing damage to active region and bit line
Solution Approach 1:
The contact hole formation process is segmented into two separate etching operations: first etching contact holes for the active region and peripheral gate region, then etching contact holes for the bit line and word line. This segmentation allows independent control of etching depth for different regions, preventing over-etching damage while maintaining process efficiency.
Solution Approach 2:
The method performs preliminary etching of contact holes for the active region and peripheral gate region before etching contact holes for the bit line and word line. By completing the first etching step with a controlled depth that stops before penetrating the oxide layer under the bit line, the patent prevents subsequent damage to the active region and bit line.
2Reliability
If etching depth is increased to reach word line and peripheral circuit, then electrical connection is achieved, but leakage current increases due to active region damage
Solution Approach 1:
The etching process is divided into two stages: the first stage creates contact holes for the active region and peripheral gate region with controlled depth, and the second stage creates contact holes for the bit line and word line. This segmentation ensures that the active region is connected without excessive etching that would cause leakage, while still achieving the necessary electrical connections.
Solution Approach 2:
The patent applies partial etching action by controlling the first etching step to reach the desired depth for active region contact without over-etching. The etching stops before penetrating the oxide layer under the bit line, applying just enough action to achieve the required electrical connection while avoiding harmful excessive etching that would increase leakage current.
3Reliability
If etching depth is increased to connect word line and peripheral circuit, then electrical connection is established, but oxide layer penetration occurs under bit line
Solution Approach 1:
The patent performs preliminary etching for the active region and peripheral gate region contact holes before etching for the bit line and word line. By controlling the depth of the first etching step to stop before penetrating the oxide layer under the bit line, the method establishes necessary electrical connections without causing harmful oxide layer penetration.
Solution Approach 2:
The etching process applies partial action by carefully controlling the etching depth to reach the word line and peripheral circuit connection point without exceeding the safe depth that would penetrate the protective oxide layer under the bit line. This precise control achieves the required electrical connection while preventing the harmful effect of oxide layer penetration.
Data Source
AI summary
A semiconductor structure and the method for forming the same are provided. The method includes: providing a substrate including an active region; forming a word line in the substrate including a first portion and a second portion located at the end of the first portion, wherein the second portion of the word line protrudes from the first portion of the word line along the direction perpendicular to the substrate; forming a dielectric layer covering the substrate; and etching the dielectric layer and a part of the substrate to simultaneously form a first contact hole exposing the second portion of the word line and a second contact hole exposing the active region. The invention reduces the etching time and improves the etching efficiency. It avoids an excessively large etching depth of the second contact hole, thereby reducing the damage to the active region and the leakage current inside the semiconductor structure.