Word Line Contact Etching With Barrier Layer Protection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge of securing reliable electrical connections between elements in semiconductor devices becomes increasingly difficult as devices are miniaturized and demand higher integration, leading to potential reliability issues in electrical connections.

Innovation Solution

A method of manufacturing semiconductor devices involves using a specific etching gas mixture of difluoromethane (CH2F2) and octafluorobutyne (C4F8) with a ratio of at least 1:1.5 to form barrier layers on exposed substrate regions, ensuring precise etching processes for contact holes, and employing multiple etching steps to create reliable connections through various layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device miniaturization and integration are increased to meet electronic device demands, then productivity and functionality are improved, but reliability of electrical connections deteriorates

Engineering Contradiction:
Improveintegration degreeVSAvoidelectrical connection reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A barrier layer is formed on the exposed logic active region surface during the etching process before subsequent processing steps. This preliminary protective action prevents contamination and damage to the logic active region, ensuring reliable electrical connections are maintained throughout further manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The barrier layer acts as an intermediary between the etching environment and the logic active region. It provides a protective interface that allows the etching process to proceed while preventing harmful effects on the underlying logic active region, thus maintaining connection reliability during miniaturization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If multiple etching processes are performed to form contact holes through various layers, then manufacturing precision is improved, but process complexity increases

Engineering Contradiction:
Improvecontact hole precisionVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Multiple etching processes are combined into a single integrated etching step that simultaneously forms both the logic active region contact hole and the word line contact hole. This merging approach maintains the precision needed for contacting different structures while reducing the overall number of separate etching processes required.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The etching process is designed to perform multiple functions simultaneously: forming contact holes through the buried insulation layer, exposing the logic active region, and creating word line contact holes. This multi-functional approach reduces process complexity while maintaining manufacturing precision for all contact structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of electrical connections by protecting sensitive substrate regions during etching, allowing for precise formation of contact plugs, thereby improving the integrity of semiconductor device performance.

Implementation Method 1

The first etching gas may include difluoromethane (CH2F2) and octafluorobutyne (C4F8), where a ratio of difluoromethane to octafluorobutyne in the first etching gas may be at least 1:1.5. The first etching process may include forming a barrier layer on the exposed logic active region of the substrate, the barrier layer being formed from the first etching gas reacting with a material of the substrate in the logic active region of the substrate that is exposed by the logic active region contact hole

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Data Source

PatentUS20260020216A1Semiconductor device and method of manufacturing the same
Publication Date: 2026.01.15 SAMSUNG ELECTRONICS CO LTD
  • US20260020216A1 patent drawing
  • US20260020216A1 patent drawing
  • US20260020216A1 patent drawing

AI summary

A method of manufacturing a semiconductor device may include sequentially forming a word line filling a word line trench of a substrate and a buried insulation layer on the word line, performing a first etching process of forming a logic active region contact hole extending to an inner portion of a logic active region of the substrate and a word line contact hole extending to an inner portion of the buried insulation layer, and performing a second etching process so that the word line contact hole extends to an inner portion of the word line. The first etching process may be performed using a first etching gas, which may include difluoromethane (CH2F2) and octafluorobutyne (C4F8) and where a ratio of difluoromethane to octafluorobutyne may be at least 1:1.5. The first etching gas may react with the logic active region to form a barrier layer.