Word Line Decoder Under 3D Memory Array
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Solution Overview
Problem
The existing three-dimensional NAND memory devices have a significant area occupancy by word line decoder circuitry and sense amplifier circuitry, which exceeds 20% of the total chip area, and is expected to increase with the number of word lines, making it desirable to reduce this fraction to enhance density and efficiency.
Innovation Solution
The solution involves locating the word line decoder circuitry and bit line decoder circuitry underneath the array of memory cells, allowing for one long side of the rectangular area to provide both bit line and word line connections, thereby reducing wiring density and the number of metal levels required, and employing a monolithic three-dimensional NAND string structure with vertical interconnection regions for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the word line decoder circuitry and sense amplifier circuitry are located in separate areas adjacent to the staircase regions, then the circuitry can be properly connected to the memory cells, but the total area occupied by these circuitry blocks exceeds 20% of the chip area and increases with the number of word lines
Solution Approach 1:
The patent moves the word line decoder circuitry from a lateral position (adjacent to staircase regions) to a vertical position (underneath the memory cell array). This dimensional change allows the decoder to share the same lateral footprint as the memory array, significantly reducing the overall chip area while maintaining all necessary electrical connections through vertical vias and conductive structures.
2Quantity of substance
If more word lines are added to increase memory density, then the storage capacity increases, but the area occupied by the word line decoder circuitry increases proportionally
Solution Approach 1:
The patent nests the word line decoder circuitry underneath the memory cell array, with the decoder positioned in the same lateral footprint as the memory cells. The decoder's output connections rise vertically through the memory array structure via conductive vias, allowing the decoder to be 'nested' within the overall memory structure rather than occupying separate lateral space.
3Reliability
If separate staircase regions are provided for word line connections, then proper electrical connection can be established, but additional wiring layers and stepped connection regions increase device complexity
Solution Approach 1:
The patent merges the word line connection structure with the existing memory array vertical interconnection structure. Instead of separate staircase regions and additional metal layers dedicated to word line connections, the decoder outputs connect vertically through the same via structures and conductive paths used for memory cell access, eliminating redundant wiring layers and simplifying the overall device architecture.
Data Source
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AI summary
The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.