Word Line Decoder Circuit With Controllable Power Supply

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Solution Overview

Problem

Conventional word line decoder circuits face issues with slow read speeds and high power consumption due to the size of PMOS transistors and inefficient power supply, affecting the selection and de-selection of word lines in memory devices.

Innovation Solution

A word line decoder circuit with a controllable power supply and optimized transistor configurations, including PMOS and NMOS transistors, is designed to provide efficient voltage control and reduce power consumption by using inversed sector select signals and separate row driver select signals to manage word line clusters and pull-down circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If PMOS transistors are made larger to improve drive strength, then word line selection speed improves, but power consumption increases

Engineering Contradiction:
Improveword line selection speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The circuit is divided into multiple local decoders, each responsible for a specific subset of word lines. This segmentation allows smaller PMOS transistors in each local decoder to achieve the required drive strength for their assigned word lines without needing oversized transistors across the entire system, thus reducing overall power consumption while maintaining selection speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each local decoder is designed with optimized transistor dimensions tailored to its specific function and the number of word lines it controls. The PMOS transistors in each local decoder are sized according to the local drive requirements rather than using uniform large-sized transistors throughout, achieving a balance between speed and power consumption.

Inventive Principle:
Principle #3Local quality

2Use of energy by moving object

If PMOS transistors are made smaller to reduce power consumption, then word line de-selection speed improves, but drive strength decreases

Engineering Contradiction:
Improvepower consumptionVSAvoiddrive strength
Core Design Contradiction:
Use of energy by moving objectVSStrength

Solution Approach 1:

By dividing the word line decoding function into multiple local decoders, each handling a subset of word lines, the circuit can use smaller PMOS transistors in each local decoder. The collective action of multiple small transistors across different local decoders provides sufficient drive strength for de-selecting word lines while consuming less power than a single large transistor would require.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple local decoders work together to control the entire set of word lines. The combined output of these local decoders provides the necessary drive strength for word line de-selection, allowing the use of smaller individual transistors that consume less power while maintaining overall system performance.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If conventional power supply is used, then circuit simplicity is maintained, but power consumption increases during word line selection

Engineering Contradiction:
Improvecircuit simplicityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The power supply circuit is made dynamic by using controllable PMOS transistors that can be turned on or off based on the current operational mode (read or write). During word line selection, the power supply is activated to provide necessary current, and during other operations, it is turned off to reduce power consumption. This dynamic power supply maintains circuit relative simplicity while significantly reducing overall power consumption.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7782705B2Word line decoder circuit
Publication Date: 2010.08.24 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
  • US7782705B2 patent drawing
  • US7782705B2 patent drawing
  • US7782705B2 patent drawing

AI summary

A word line decoder circuit is provided in the present invention. The word line decoder circuit comprises at least one local pre-decoder, at least one 3-transistors row driver, a controllable power supply, and a controllable pull-down circuit. The controllable power supply is controlled by an inversed sector select signal to provide a first voltage to the row driver and local pre-decoder. The local pre-decoder uses 5-transistors architecture, in which there are 2 PMOS transistors and 3 NOS transistors. The controllable pull-down circuit pulls down the local pre-decoder and is controlled by a sector select signal and pre-decoding signal. The local pre-decoder receives a local pre-decoding signal to select the row driver. When the row driver is selected, the row driver determines a word line according to a row driver pull-down signal and a row driver pull-up signal.