Word Line Decoder Architecture Reducing Propagation Delay

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Solution Overview

Problem

Conventional word line decoder and driver path architectures in computing systems experience significant propagation delays, hindering the speed of memory devices and necessitating an improvement to enhance memory access times.

Innovation Solution

The proposed solution involves a memory device architecture that includes a level shifter latch and driver, utilizing a short pulse clock signal to decode address signals and drive word lines, which reduces propagation delays by optimizing the level shifting and driving mechanisms, eliminating the need for clocked flip flops and minimizing circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional word line decoder and driver path architecture is used, then the memory device can operate, but the propagation delay is significant and memory access speed is limited

Engineering Contradiction:

Improvememory access speedVSAvoidpropagation delay

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The word line driver circuit is segmented into multiple independent parallel paths, each handling a portion of the decoded address signals. This segmentation allows simultaneous processing of multiple signals, reducing overall propagation delay and improving memory access speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Decoded address signals are pre-latched and prepared in advance using latch circuits before being transmitted to the word line drivers. This preliminary action ensures that data is ready for immediate transmission, minimizing waiting time and reducing overall propagation delay.

Inventive Principle:

Principle #10Preliminary action

2Device complexity

If conventional clocked flip flops are used for latching, then the address can be latched, but the circuit area and complexity increase

Engineering Contradiction:

Improvecircuit complexityVSAvoidlatching function

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent uses simple latch circuits instead of complex clocked flip-flop circuits. These latches are designed to be simpler, smaller, and less complex while still performing the essential latching function reliably, thereby reducing circuit area and complexity.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

Instead of using complex clocked flip-flops that require multiple gates and feedback paths, the invention employs simplified latch structures that achieve the same latching effect with fewer components, inverting the conventional approach to latching circuit design.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS11423965B2Word line decoder memory architecture

Publication Date: 2022.08.23 INTEGRATED SILICON SOLUTION CAYMAN INC

AI summary

A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.