Semiconductor Memory Word Line Decoder Self-Boosting Circuit
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Solution Overview
Problem
Conventional NAND type flash memory word line decoders face challenges in reducing chip area and power consumption due to increased resistance-capacitance (RC) of word lines, high voltage requirements, and potential latch-up issues, which lead to increased transistor size and circuit area.
Innovation Solution
A semiconductor memory device with a word line decoder and drive circuit that utilizes self-boosting transistors to raise voltage levels, eliminating the need for a charge pump and reducing the layout scale, while arranging the word line drive circuit between memory arrays to minimize wire length and electric field influence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a charge pump is used to raise voltage levels in the word line decoder, then the voltage level of word line enable signal can be raised, but the layout scale of the word line decoder increases substantially due to capacitors
Solution Approach 1:
The patent extracts and removes the charge pump circuit from the word line decoder, eliminating the need for large capacitors while maintaining voltage boosting capability through alternative means
Solution Approach 2:
The word line decoder is designed to self-boost the voltage level of word line enable signals using its own internal circuitry without requiring external charge pump assistance, thereby reducing layout scale while maintaining functionality
2Use of energy by moving object
If a charge pump is used to raise the voltage level of program voltage or read voltage, then voltage can be boosted, but threshold voltages of NMOS transistors increase due to body effect, resulting in difficulty to sufficiently raise voltages
Solution Approach 1:
The patent introduces an intermediate voltage boosting mechanism that operates between the charge pump and the NMOS transistors, using self-boosting circuitry to raise voltages without directly affecting the body effect on transistor threshold voltages
3Device complexity
If the word line decoder is arranged at one end of the memory array, then circuit layout is simplified, but wire length increases leading to increased RC and potential latch-up issues
Solution Approach 1:
The patent positions the word line drive circuit in the space between memory arrays (utilizing the vertical dimension), which reduces horizontal wire length and associated RC effects while maintaining layout simplicity
4Reliability
If transistor size is increased to prevent latch-up issues, then reliability improves, but chip area increases
Solution Approach 1:
The patent removes the word line drive circuit from the traditional end-position layout and places it between memory arrays, which reduces wire length and allows for smaller transistor sizes while maintaining latch-up immunity
Solution Approach 2:
The patent changes the spatial parameter of the word line drive circuit position from 'at end of array' to 'between arrays', which fundamentally alters the electrical characteristics and allows for reduced transistor dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the voltage applied to transistors, minimizes transistor size, and eliminates the need for a charge pump, thereby decreasing the chip area and power consumption while preventing voltage lowering and latch-up issues.
Implementation Method 1
a switch circuit switching operation voltages to be supplied to the memory cells according to the selecting signal, and a voltage booster circuit boosting the voltage level of the selecting signal, wherein the switch circuit includes at least one transistor self-boosting the voltage level of the selecting signal according to the operation voltage
Data Source
AI summary
A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing a chip area, includes a memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block in the memory array according to an address signal, and outputting a selecting signal to the selected memory block, and a word line drive circuit 130 comprising a switch circuit arranged between the memory arrays 110A and 110B and switching the application of the work voltage to a memory cell according to the selecting signal, and a pump circuit raising the voltage level of the selecting signal. The word line decoder 120 has lines WR(i) to transmit the selecting signals. The lines WR(i) are connected to the switch circuit of the word line drive circuit 130.