Word Line Defect Detection Circuit Using Pump Clock Comparison

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Solution Overview

Problem

As memory devices shrink, defects such as bridge defects between electrical connections become more prevalent, deteriorating operating performance and requiring effective detection methods to ensure reliability.

Innovation Solution

Incorporating a word line defect detection circuit with a clock generator, charge pump, compensation circuit, and pass/fail determining circuit to compare pumping clock signals and compensated reference clock signals, allowing for the identification of defective word lines by analyzing pulse counts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory devices are shrunk to increase storage density, then storage capacity is improved, but defect rate increases due to reduced distance between electrical connections

Engineering Contradiction:
Improvestorage capacityVSAvoiddefect rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent performs word line defect detection before normal memory operations by applying program voltages and comparing pumping clock signals during an initialization phase. This preliminary detection identifies defective word lines early, preventing them from causing errors during subsequent read/write operations, thus maintaining reliability while enabling continued miniaturization for higher storage capacity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The defect detection circuit uses the memory device's own internal components (charge pump, word lines, memory cells) to perform self-diagnosis. The pumping clock signal generated by the internal charge pump is compared against a reference clock signal to detect defects, eliminating the need for external testing equipment and enabling automated reliability verification during manufacturing or initialization.

Inventive Principle:
Principle #25Self-service

2Reliability

If a defect detection circuit is added to improve reliability, then detection capability is improved, but device complexity increases

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The detection circuit reuses existing memory device components for multiple purposes: the charge pump serves both normal voltage generation and defect detection timing functions, memory cells are used as test elements during detection, and word lines serve both data access and defect identification roles. This multi-functionality enables defect detection without adding separate dedicated testing hardware, thus improving reliability while limiting complexity increase.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces a reference clock signal as an intermediary standard for comparison against the pumping clock signal. This reference signal acts as a mediator that enables accurate defect detection by providing a stable baseline for timing comparison, allowing the system to identify deviations caused by defective word lines without requiring complex direct measurement circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If pumping voltage is applied to detect defects, then detection accuracy is improved, but power consumption increases

Engineering Contradiction:
Improvedefect detection accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The defect detection is performed periodically during initialization or idle periods by applying program voltages that generate pumping clock signals. The detection operates in discrete cycles rather than continuously, applying voltage only when needed for detection purposes. This periodic operation enables accurate defect identification while limiting power consumption to specific time windows, preventing continuous high-power draw during normal memory operations.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10482973B2Memory devices including a word line defect detection circuit
Publication Date: 2019.11.19 SAMSUNG ELECTRONICS CO LTD
  • US10482973B2 patent drawing
  • US10482973B2 patent drawing
  • US10482973B2 patent drawing

AI summary

A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.