Word Line Discharge Sequence for Memory Cell Stability

Solution Overview

Problem

Existing memory devices face challenges in managing negative boosting during word line discharge operations, which can lead to disturbances in threshold voltages of memory cells.

Innovation Solution

The memory device includes a memory cell string with multiple memory cells coupled to word lines, a peripheral circuit for applying operating and pass voltages, and an operation controller that performs a discharge operation, sequentially decreasing voltages from a central word line to outermost word lines adjacent to a select line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If word line discharge operation is performed to reset voltages after memory operation, then voltage levels are restored for next operation, but negative boosting occurs causing threshold voltage disturbances in memory cells

Engineering Contradiction:
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by maintaining pass voltages on unselected word lines during the discharge operation. Specifically, the peripheral circuit keeps certain word lines at pass voltage levels while others are discharged to ground, preventing negative boosting effects before they can disturb memory cell threshold voltages. This preparatory voltage maintenance approach eliminates the harmful negative boosting phenomenon that would otherwise occur during complete voltage discharge.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If discharge operation is performed to prepare word lines for next operation, then memory device can perform subsequent operations, but channel cutoff occurs reducing operation reliability

Engineering Contradiction:
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent prevents channel cutoff by maintaining pass voltages on specific unselected word lines during the discharge operation. The operation controller coordinates the peripheral circuit to keep certain word lines at elevated voltage levels while others discharge, ensuring that memory cell channels remain conductive and ready for immediate subsequent operations without reliability degradation.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If complete discharge of all word lines is performed, then voltage levels are fully reset for next operation, but negative boosting and channel cutoff occur simultaneously

Engineering Contradiction:
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the word line discharge operation into multiple groups: word lines that are discharged to ground potential and word lines that maintain pass voltages. The operation controller selectively discharges only certain word lines while keeping others at elevated potentials, thereby achieving voltage reset for operated word lines without causing negative boosting or channel cutoff in the entire memory cell array. This segmented approach allows complete voltage reset where needed while preventing harmful effects in other regions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12283323B2Memory device and method of operation with sequential discharging of word lines
Publication Date: 2025.04.22
  • US12283323B2 patent drawing
  • US12283323B2 patent drawing
  • US12283323B2 patent drawing

AI summary

Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell string including a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform an operation that applies an operating voltage to a selected word line and applying a pass voltage to unselected word lines, among the plurality of word lines, and an operation controller configured to control the peripheral circuit to perform, after the operation has been performed, a discharge operation that sequentially decreases voltages of the plurality of word lines that range from at least one central word line located in a central portion in relation to the memory cell string to a word line, among the plurality of word lines, located in an outermost portion in relation to the memory cell string, adjacent to a select line.