Word Line Discharge Sequencing for Memory Power-Drop Disturbance
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Solution Overview
Problem
Semiconductor memory devices face disturbances due to sudden reductions in external power supply voltage, leading to variations in word line discharge times and channel boosting levels, which affect the stability and efficiency of memory cell operations.
Innovation Solution
A semiconductor memory device with a voltage generation circuit and control logic that manages word line discharge operations by controlling the potential levels of selected and unselected word lines during power reductions, ensuring differential discharge periods and ultimately discharging all word lines to ground level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If word lines are discharged simultaneously when external power supply voltage is reduced, then discharge operation is simple, but disturbance phenomenon occurs due to variations in channel boosting levels
Solution Approach 1:
The patent segments the word line discharge operation into two distinct phases: first discharging only the selected word line, then discharging the unselected word lines. This segmentation prevents simultaneous discharge that causes disturbance while maintaining operational simplicity through controlled sequencing.
Solution Approach 2:
The patent applies preliminary action by first discharging the selected word line before discharging the unselected word lines. This preliminary discharge of the selected word line prevents channel boosting disturbance that would occur if all word lines were discharged simultaneously, while still maintaining a relatively simple two-stage discharge process.
2Use of energy by moving object
If external power supply voltage is reduced during program operation, then power consumption is reduced, but disturbance phenomenon occurs affecting memory cell operation
Solution Approach 1:
The patent applies preliminary anti-action by implementing a specific discharge sequence that counteracts the disturbance effect. When external power supply voltage is reduced, the selected word line is discharged first, which prevents channel boosting in memory cells connected to unselected word lines, thereby mitigating the disturbance phenomenon that would otherwise occur during power reduction.
3Speed
If potential levels of all word lines are discharged to ground level simultaneously, then discharge is complete and fast, but channel boosting levels vary causing disturbance
Solution Approach 1:
The patent segments the discharge process into two sequential stages: first stage discharges only the selected word line to ground level, second stage discharges unselected word lines to ground level. This segmentation maintains fast discharge speed while ensuring channel boosting consistency by preventing simultaneous discharge that causes varying boosting levels.
Solution Approach 2:
The patent applies preliminary action by first discharging the selected word line before discharging unselected word lines. This preliminary discharge ensures that memory cells connected to the selected word line are properly discharged first, preventing channel boosting disturbances while maintaining efficient overall discharge performance.
Data Source
AI summary
A semiconductor memory device includes a memory cell array to which a plurality of word lines are coupled, a voltage generation circuit configured to apply operating voltages to the plurality of word lines during a program operation, and a control logic configured to control the voltage generation circuit to perform a discharge operation for the plurality of word lines when an external power supply voltage is reduced during the program operation, wherein the control logic controls the voltage generation circuit such that, during the discharge operation, a potential level of a selected word line among the plurality of word lines is discharged, and then potential levels of the other unselected word lines are discharged.