Word Line Driver Circuit Erase Disturb Control
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Solution Overview
Problem
Traditional memory designs face issues with erase disturb in deselected word lines and complex logic for coupling word lines to various voltages, which complicates signal control and affects memory operations.
Innovation Solution
The solution involves a memory circuit with control circuitry that couples deselected word lines to a reference voltage during an erase operation, and switchably couples word lines to a global word line or ground voltage, depending on selection status, to prevent erase disturb and simplify voltage logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deselected word lines are left floating during erase operation, then the word line driver circuit is simple, but erase disturb occurs from proximate selected word lines
Solution Approach 1:
The patent segments the word line driver circuit into separate control paths: one for selected word lines and one for deselected word lines. The deselected word lines are coupled to a reference voltage through dedicated control circuitry, while selected word lines are coupled to a high voltage. This segmentation allows independent control of each word line type, preventing erase disturb without requiring complete redesign of the driver circuit.
Solution Approach 2:
The patent introduces a reference voltage as an intermediary element between the ground and the deselected word lines. Instead of directly coupling deselected word lines to ground or leaving them floating, the reference voltage serves as a stable intermediary that prevents erase disturb while maintaining circuit simplicity. The control circuitry acts as another intermediary to manage the coupling between the reference voltage and deselected word lines.
2Device complexity
If logic for coupling word line to various voltages is located with row decoder, then word line driver circuit is simple, but control signals become complex
Solution Approach 1:
The patent segments the control logic into distinct modules: row decoder logic for address decoding, word line driver logic for voltage coupling, and control circuitry for coordinating between them. The control circuitry receives simplified control signals from the row decoder and translates them into appropriate voltage coupling actions, separating the complexity of address decoding from the simplicity of driver control signals.
Solution Approach 2:
The control circuitry acts as an intermediary between the row decoder and the word line driver. It receives control signals from the row decoder, processes them through intermediate logic, and generates simplified control signals for the word line driver. This intermediary layer absorbs the complexity of signal generation while presenting simple control interfaces to both the row decoder and word line driver.
Data Source
AI summary
A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.