Word Line Driver Discharge Control for Memory Circuits
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Solution Overview
Problem
Existing two-transistor (2T) word line drivers in memory integrated circuits face challenges with transistor gate dielectric stress due to electric field, leading to inadequate discharge of word lines without negative input bias, resulting in prolonged switching times and inefficiencies.
Innovation Solution
The implementation of a memory circuit with CMOS inverters and control circuitry that allows for multiple modes of operation, utilizing both p-type and n-type transistors to discharge word lines, where the control circuitry can selectively use either transistor type to manage capacitive coupling and reduce unwanted voltage durations on deselected word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a 2T word line driver is used to discharge a word line through the p-type transistor, then the device structure is simplified, but the transistor gate dielectric undergoes great electric field stress and the discharge is incomplete without negative input bias
Solution Approach 1:
The patent segments the word line driver into multiple independent driver circuits, each capable of driving a subset of word lines. This segmentation allows each driver to be optimized independently and reduces the stress on individual transistors by distributing the discharge current across multiple devices.
Solution Approach 2:
The patent applies different transistor types (n-type and p-type) in different locations within the same driver circuit. The n-type transistors are used for discharging selected word lines while p-type transistors handle other operations, allowing each transistor type to operate in its optimal performance range and reducing gate dielectric stress.
2Reliability
If negative input bias is applied to the p-type transistor to enable complete discharge, then the discharge function is improved, but the power consumption increases and the operation complexity increases
Solution Approach 1:
Instead of applying negative bias to the p-type transistor to enable discharge, the patent inverts the approach by using the n-type transistor to perform the discharge function. The n-type transistor naturally provides strong discharge capability without requiring negative bias, thereby achieving complete word line discharge while avoiding the power consumption and complexity associated with negative bias generation.
3Device complexity
If the p-type transistor is used to discharge deselected word lines, then the discharge path is simplified, but the discharge speed is slow due to the inherent characteristics of p-type transistors
Solution Approach 1:
The patent changes the key parameter of the discharge path by selecting different transistor types based on the operational requirements. For discharging deselected word lines where speed is critical, the patent uses n-type transistors which have higher electron mobility and faster switching characteristics compared to p-type transistors, thereby significantly improving discharge speed.
4Device complexity
If adjacent word lines are not properly deselected during memory operations, then the control logic is simplified, but capacitive coupling causes unwanted voltage on deselected word lines extending into the next operation
Solution Approach 1:
The patent implements preliminary deselecting of adjacent word lines before the main memory operation begins. By proactively discharging adjacent word lines through appropriate discharge paths using n-type transistors, the patent ensures that these word lines are fully discharged and ready for the next operation, preventing capacitive coupling effects from extending into subsequent operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances discharge speed and efficiency by preventing discharge through the p-type transistor for deselected word lines, thereby reducing switching times and improving overall memory operation performance.
Implementation Method 1
decreases the duration of time in which a deselected word line proximate to the selected word line has an unwanted voltage due to capacitive coupling between the selected word line and the deselected word line
Data Source
AI summary
A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter.