Multi-Port Memory Word Line Driver Priority Arbitration
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Solution Overview
Problem
In multiple port semiconductor memories, data contention occurs when two or more write word lines are enabled simultaneously, leading to incorrect data values, increased power consumption, and transistor integrity issues due to high current flow, and existing solutions like comparator-based address decoding are inefficient and slow.
Innovation Solution
The implementation of a word line driver circuit that generates predecoded addresses to ensure only one write word line is asserted per row, eliminating the need for full-address comparison and reducing data contention by prioritizing write access through dynamic priority selection and disable signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comparator-based address decoding circuitry is used to detect address collisions, then data write contentions are avoided, but device complexity and power consumption increase significantly
Solution Approach 1:
The patent extracts the collision detection function from complex comparator-based address decoding circuitry and implements it through simplified word line driver logic that monitors write word line assertion states. This removes the need for extensive comparison operations while maintaining contention detection capability.
Solution Approach 2:
The word line drivers perform self-monitoring of their own assertion states and automatically detect potential contentions through inter-driver signaling. The system uses the drivers' own operational states to trigger arbitration, eliminating the need for separate external monitoring circuitry.
2Reliability
If full-address comparison operations are performed to detect address collisions, then data write contentions are prevented, but memory cycle time increases
Solution Approach 1:
The patent performs preliminary contention detection by monitoring write word line assertion states before complete address comparison is finished. The arbitration logic is triggered early based on write word line signals, allowing parallel execution of address comparison and contention detection without sequential delays.
Solution Approach 2:
The system maintains continuous contention monitoring through ongoing watchdog timer operation and persistent monitoring of write word line states. This eliminates idle time during memory cycles by keeping the arbitration mechanism continuously active rather than activating it only when collisions are detected.
3Productivity
If multiple write word lines are enabled simultaneously to different memory cells, then write throughput increases, but data contention occurs at the same memory cell
Solution Approach 1:
The patent introduces an intermediary arbitration logic circuit that mediates between multiple write ports and the memory array. This intermediary monitors write word line signals and coordinates access to prevent simultaneous writes to the same memory cell while maintaining high throughput through efficient arbitration.
Solution Approach 2:
The system implements feedback mechanisms where the arbitration logic continuously monitors write word line assertion states and adjusts port enabling accordingly. The watchdog timer provides feedback to detect and respond to contention conditions, dynamically controlling which ports can write to maintain both throughput and data integrity.
4Reliability
If arbitration logic circuit is used to prioritize port access, then data write contention is resolved, but device complexity increases
Solution Approach 1:
The patent implements arbitration functionality locally within each word line driver rather than using a centralized complex arbitration unit. Each driver has integrated logic to monitor its own write word line assertion state and participate in contention resolution, distributing the arbitration function across multiple simple local units rather than one complex central unit.
Data Source
AI summary
A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a first port selection signal, a second input for receiving a disable signal, and an output. A buffer circuit has an input coupled to the output of the first logic circuit, and an output for providing the word line signal. The disable signal is asserted to prevent the word line driver from accessing the first write port when a second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port.