Word-Line Driver With Segmented Power Supplies

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Solution Overview

Problem

Conventional word-line drivers in semiconductor memory designs experience significant leakage power in standby mode due to large transistors in the output stages, which leads to inefficient power usage and slow wake-up times when transitioning to active mode.

Innovation Solution

The word-line driver employs separate internal power supplies for decoder logic modules and output stages, and includes pull-down circuitry to quickly power down and power up the output stages, ensuring fast wake-up and minimizing leakage power by using a sleep signal to control transistor states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If large transistors are used in output stages to drive word lines, then the word line can be driven with sufficient current, but leakage power increases significantly in standby mode

Engineering Contradiction:
Improveword line driving capabilityVSAvoidleakage power
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

The patent divides the word-line driver into separate functional blocks: decoder logic modules and output stages, each with independent power supplies. This segmentation allows the output stages to be completely powered down in standby mode while keeping the decoder active, eliminating the leakage path through large transistors while preserving driving capability when needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic power control by introducing separate power supplies for different parts of the circuit and using sleep signals to dynamically enable/disable power delivery to output stages. This allows the system to transition between low-power standby mode (output stages off) and high-power active mode (output stages on) as needed.

Inventive Principle:
Principle #15Dynamics

2Speed

If output stages are kept active to ensure fast response, then wake-up time is reduced, but leakage power consumption increases

Engineering Contradiction:
Improvewake-up speedVSAvoidleakage power
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by keeping the decoder logic modules powered on and ready in advance, so that when wake-up is needed, the decoding function is immediately available. The output stages are quickly enabled through the sleep signal mechanism, minimizing the time they spend in transition and thus reducing energy loss during wake-up.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the decoding function from the output stages by separating the decoder logic modules into an independent block with its own power supply. This allows the decoder to remain active while output stages are powered down, and vice versa, optimizing the balance between wake-up speed and power consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of energy

If separate power supplies are used for decoder and output stages, then leakage power is reduced, but device complexity increases

Engineering Contradiction:
Improveleakage powerVSAvoidpower supply structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements multi-functionality by designing the separate power supply structure to serve multiple purposes: it provides independent power control for leakage reduction, enables dynamic wake-up capability, and allows different voltage levels for different functional blocks. This universal design approach justifies the added complexity through multiple benefits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11721380B2Word-line driver and method of operating a word-line driver
Publication Date: 2023.08.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11721380B2 patent drawing
  • US11721380B2 patent drawing
  • US11721380B2 patent drawing

AI summary

Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.